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11. 发明授权

US08627048B2 Mechanism for irrevocable transactions 有权
标题翻译：不可撤销交易的机制
公开(公告)号：US08627048B2
公开(公告)日：2014-01-07
申请号：US13231575
申请日：2011-09-13
申请人： Adam Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Adam Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/00
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087 , G06F9/3857 , G06F9/3863
摘要： A method and apparatus for designating and handling irrevocable transactions is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designated as irrevocable. In response to designating a transaction as irrevocable, Single Owner Read Locks (SORLs) are acquired for previous and subsequent reads in the irrevocably designated transaction to ensure the transaction is able to complete without modification to locations read from, while permitting remote resources to load from those locations to continue execution.
摘要翻译：这里描述用于指定和处理不可撤销交易的方法和装置。响应于检测到诸如I / O操作，用户定义的不可撤销指定和动态故障简档的不可撤销事件，交易被指定为不可撤销。为了将交易指定为不可撤销，单独所有者读取锁（SORL）是为不可撤销地指定的事务中的先前和后续读取而获取的，以确保事务能够完成，而无需修改读取的位置，同时允许远程资源从那些位置继续执行。

12. 发明授权

US08195898B2 Hybrid transactions for low-overhead speculative parallelization 有权
标题翻译：低架构投机并行化的混合交易
公开(公告)号：US08195898B2
公开(公告)日：2012-06-05
申请号：US11965120
申请日：2007-12-27
申请人： Adam Welc , Ali-Reza Adl-Tabatabai
发明人： Adam Welc , Ali-Reza Adl-Tabatabai
IPC分类号： G06F13/14
CPC分类号： G06F9/467
摘要： A method and apparatus for a hybrid transactional memory system is herein described. A first transaction is executed utilizing a first style of a transactional memory system and a second transaction is executed in parallel utilizing a second style of a transactional memory system. For example, a main thread is executed utilizing an update-in place Software Transactional Memory (STM) system while a parallel thread, such as a helper thread, is executed utilizing a write buffering STM. As a result, a main thread may directly update memory locations, while a helper thread's transactional writes are buffered to ensure they do not invalidate transactional reads of the main thread. Therefore, parallel execution of threads is achieved, while ensuring at least one thread, such as a main thread, does not degrade below an amount of execution cycles it would take to execute the main thread serially.
摘要翻译：这里描述了用于混合事务存储器系统的方法和装置。使用事务性存储器系统的第一种类型执行第一事务，并且使用事务存储器系统的第二种类型来并行地执行第二事务。例如，利用写入缓冲STM执行诸如辅助线程的并行线程，利用更新软件事务存储器（STM）系统来执行主线程。因此，主线程可以直接更新内存位置，而辅助线程的事务写入被缓冲，以确保它们不会使主线程的事务读取无效。因此，实现线程的并行执行，同时确保至少一个线程（例如主线程）不会降级到低于执行连续执行主线程所需的执行周期数量。

13. 发明申请

US20090319753A1 HYBRID LINEAR VALIDATION ALGORITHM FOR SOFTWARE TRANSACTIONAL MEMORY (STM) SYSTEMS 有权
标题翻译：用于软件交互式存储器（STM）系统的混合线性验证算法
公开(公告)号：US20090319753A1
公开(公告)日：2009-12-24
申请号：US12142097
申请日：2008-06-19
申请人： Adam Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
发明人： Adam Welc , Bratin Saha , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/06
CPC分类号： G06F9/526 , G06F9/466
摘要： A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation.
摘要翻译：这里描述了用于软件事务存储器（STM）的混合验证的方法和装置。在执行事务期间，当获取与数据元素相关联的元数据的所有权时，元数据被更新为对事务的所有权引用，以便能够进行有效的后续所有权测试。然而，在验证期间，对于某些条件，元数据从所有权引用更新为写入条目引用以实现高效验证。

14. 发明申请

US20090172303A1 HYBRID TRANSACTIONS FOR LOW-OVERHEAD SPECULATIVE PARALLELIZATION 有权
标题翻译：用于低通量测量并联的混合交易
公开(公告)号：US20090172303A1
公开(公告)日：2009-07-02
申请号：US11965120
申请日：2007-12-27
申请人： Adam Welc , Ali-Reza Adl-Tabatabai
发明人： Adam Welc , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00 , G06F9/46
CPC分类号： G06F9/467
摘要： A method and apparatus for a hybrid transactional memory system is herein described. A first transaction is executed utilizing a first style of a transactional memory system and a second transaction is executed in parallel utilizing a second style of a transactional memory system. For example, a main thread is executed utilizing an update-in place Software Transactional Memory (STM) system while a parallel thread, such as a helper thread, is executed utilizing a write buffering STM. As a result, a main thread may directly update memory locations, while a helper thread's transactional writes are buffered to ensure they do not invalidate transactional reads of the main thread. Therefore, parallel execution of threads is achieved, while ensuring at least one thread, such as a main thread, does not degrade below an amount of execution cycles it would take to execute the main thread serially.
摘要翻译：这里描述了用于混合事务存储器系统的方法和装置。使用事务性存储器系统的第一种类型执行第一事务，并且使用事务存储器系统的第二种类型来并行地执行第二事务。例如，利用写入缓冲STM执行诸如辅助线程的并行线程，利用更新软件事务存储器（STM）系统来执行主线程。因此，主线程可以直接更新内存位置，而辅助线程的事务写入被缓冲，以确保它们不会使主线程的事务读取无效。因此，实现线程的并行执行，同时确保至少一个线程（例如主线程）不会降级到低于执行连续执行主线程所需的执行周期数量。

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