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    • 19. 发明申请
    • SEMICONDUCTOR MEMORY AND SYSTEM
    • 半导体存储器和系统
    • US20120087172A1
    • 2012-04-12
    • US13240492
    • 2011-09-22
    • Masaki Aoki
    • Masaki Aoki
    • G11C11/00
    • G11C13/003G11C11/16G11C11/1659G11C11/1673G11C11/1675G11C13/0004G11C13/0007G11C13/004G11C29/021G11C29/028G11C2213/79
    • A semiconductor memory includes a real memory cell including a selection transistor and a resistance variable element which are connected in series between a first voltage line and a second voltage line through a connection node, a real amplification transistor having a gate connected to the connection node, a source connected to a reference voltage line, and a drain connected to a real read line, and a sense amplifier to determine a logic held in the real memory cell by receiving a voltage of the real read line varied with a voltage generated in the connection node by resistance dividing between a source/drain resistance of the selection transistor, and the resistance variable element, the selection transistor receiving a read control voltage at the gate thereof.
    • 半导体存储器包括:实际存储单元,包括通过连接节点串联连接在第一电压线和第二电压线之间的选择晶体管和电阻可变元件,具有连接到连接节点的栅极的实际放大晶体管, 连接到参考电压线的源极和连接到实际读取线的漏极,以及读出放大器,用于通过接收由连接中产生的电压而变化的真实读取线的电压来确定保持在实际存储单元中的逻辑 所述选择晶体管在所述栅极处接收读取控制电压,所述选择晶体管在所述栅极处接收读取控制电压。