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    • 11. 发明授权
    • Rotary cutter for mower
    • 割草机旋转切割机
    • US08069574B2
    • 2011-12-06
    • US12382315
    • 2009-03-13
    • Hiroki KatoTetsuya Yamada
    • Hiroki KatoTetsuya Yamada
    • A01D34/416
    • A01D34/416
    • A rotary cutter for a mower is described including at least one cord of a predetermined length extending from the cutting head driven for rotation, and at least one fastening element for fixing one end of the cord to the cutting head main body. The fastening element includes a pair of ratchets. Each ratchet pivots for turning on the main body and is constantly applied with a rotational force in a predetermined direction by a spring. The cord is clamped and fastened by the ratchets. An inner end portion of the cord inserted from the sidewall of the main body is fastened by the fastening element, and the cord is removed and replaced with a new cord when the cord is worn out. The fastening element including a pair of ratchets with each ratchet of the pair including at least two or more sheets of laminated ratchets.
    • 描述了一种用于割草机的旋转切割机,其包括从被驱动旋转的切割头延伸的至少一根预定长度的绳索和用于将绳索的一端固定到切割头主体的至少一个紧固元件。 紧固元件包括一对棘爪。 每个棘轮枢转以转动主体,并通过弹簧不断地施加预定方向的旋转力。 绳被夹紧并由棘轮固定。 从主体的侧壁插入的帘线的内端部由紧固元件固定,并且当绳索被磨损时,绳索被移除并用新的线替换。 紧固元件包括一对棘轮,每对棘轮包括至少两个或多个层压棘轮。
    • 12. 发明申请
    • INFORMATION PROCESSING DEVICE
    • 信息处理设备
    • US20110238883A1
    • 2011-09-29
    • US13062508
    • 2009-08-04
    • Hiroaki NakayaTetsuya YamadaNaoki Kato
    • Hiroaki NakayaTetsuya YamadaNaoki Kato
    • G06F13/20
    • G06F9/30018G06F9/30043
    • An information processing device is provided, in which a bit operation is performed without degradation in performance of a bus. An information processing device includes a CPU which fetches and executes an instruction, and a peripheral module which includes internally a register rewritable by the CPU, and is coupled to the CPU via a bus. The CPU has a function of issuing a bus command for commanding a bitwise write operation to the register comprised in the peripheral module, in order to execute a bit operation command fetched. When the bus command is issued, the peripheral module executes a bitwise write operation for the register. Since the CPU does not need to lock the bus after the bus command is issued, a bit operation can be performed without degradation in performance of the bus.
    • 提供一种信息处理装置,其中执行位操作而不会降低总线的性能。 信息处理装置包括取出并执行指令的CPU以及内部包含CPU可重写的寄存器的外围模块,并通过总线耦合到CPU。 CPU具有发出用于对包含在外围模块中的寄存器进行逐位写入操作的总线命令的功能,以便执行读取的位操作命令。 当发出总线命令时,外设模块对寄存器执行逐位写操作。 由于CPU在总线命令发出后不需要锁定总线,所以可以执行位操作而不会降低总线性能。
    • 13. 发明授权
    • Semiconductor integrated circuit device and power consumption control device
    • 半导体集成电路器件和功耗控制器件
    • US07646197B2
    • 2010-01-12
    • US11542133
    • 2006-10-04
    • Satoshi MisakaMakoto SaenTetsuya YamadaKeisuke ToyamaKenichi Osada
    • Satoshi MisakaMakoto SaenTetsuya YamadaKeisuke ToyamaKenichi Osada
    • G01V3/00
    • G06F1/3203G06F1/329Y02D10/24Y02D50/20
    • To perform execution scheduling of function blocks so as to control the total required power of the function blocks within a supplyable power budget value, and thereby realize stable operations at low power consumption. Function block identifiers are allotted to all the function blocks, and to a RAM area that a power consumption control device can read and write, a list to store identifiers and task priority, power mode value showing power states, and power mode time showing the holding time of power states can be linked. A single or plural link lists for controlling the schedules of tasks operating on the function blocks, a link list for controlling the function block in execution currently in high power mode, a link list for controlling the function block in stop currently in stop mode, and a link list for controlling the function block in execution currently in low power mode are allotted, and thereby the power source and the operation clock are controlled by the power consumption control device.
    • 执行功能块的执行调度,以便在可供电功率预算值内控制功能块的总需求功率,从而在低功耗下实现稳定的操作。 功能块标识符分配给所有功能块,以及功率控制装置可以读写的RAM区域,存储标识符和任务优先级的列表,显示功率状态的功率模式值和显示保持的功率模式时间 电力状态的时间可以联系起来。 用于控制在功能块上操作的任务的调度的单个或多个链接列表,用于控制当前处于高功率模式的执行中的功能块的链接列表,用于控制当前处于停止模式的停止功能块的链接列表,以及 分配用于控制当前处于低功率模式的执行功能块的链接列表,从而由功耗控制装置控制电源和操作时钟。
    • 14. 发明申请
    • DATA PROCESSOR
    • 数据处理器
    • US20090271576A1
    • 2009-10-29
    • US12414656
    • 2009-03-30
    • Tetsuya YamadaNaoki KatoKesami Hagiwara
    • Tetsuya YamadaNaoki KatoKesami Hagiwara
    • G06F12/02
    • G06F9/383G06F9/30043G06F9/322G06F9/355G06F9/3802G06F12/0862G06F2212/6028
    • There is a need for providing a data processor capable of easily prefetching data from a wide range. A central processing unit is capable of performing a specified instruction that adds an offset to a value of a register to generate an effective address for data. This register can be assigned an intended value in accordance with execution of an instruction. A buffer maintains part of instruction streams and data streams stored in memory. The buffer includes cache memories for storing the instruction stream and the data stream. From the memory, the buffer prefetches a data stream containing data corresponding to an effective address designated by the specified instruction stored in the cache memory. A data prefetch operation is easy because a data stream is prefetched by finding the specified instruction from the fetched instruction stream. Data can be prefetched from a wider range than the use of a PC-relative load instruction.
    • 需要提供能够容易地从大范围预取数据的数据处理器。 中央处理单元能够执行向寄存器的值添加偏移量的指定指令,以生成数据的有效地址。 可以根据指令的执行为该寄存器分配预期值。 缓冲器保持存储在存储器中的指令流和数据流的一部分。 缓冲器包括用于存储指令流和数据流的高速缓冲存储器。 从存储器中,缓冲器预取包含对应于存储在高速缓冲存储器中的指定指令指定的有效地址的数据的数据流。 数据预取操作很容易,因为通过从获取的指令流中找到指定的指令来预取数据流。 数据可以从比使用PC相关负载指令的范围更广泛地预取。
    • 16. 发明申请
    • MICROCONTROLLER AND CONTROLLING SYSTEM
    • 微控制器和控制系统
    • US20090113186A1
    • 2009-04-30
    • US12262173
    • 2008-10-30
    • Naoki KATOTetsuya YamadaFumio ArakawaHiromichi YamadaShigeru OhoMakoto Ishikawa
    • Naoki KATOTetsuya YamadaFumio ArakawaHiromichi YamadaShigeru OhoMakoto Ishikawa
    • G06F9/22G06F7/42G06F3/00
    • G06F9/30025G06F7/483G06F9/3001H03M7/24
    • A microcontroller and a controlling system having the same are provided, in which the increase in the program code for performing floating-point arithmetic, in particular, the increase in the amount of code due to a variable are suppressed, and the processing overhead for converting fixed-point data into floating-point data is reduced. The microcontroller includes a floating-point converter which inputs integer data and corresponding decimal point position data as fixed-point data and which converts the input data into floating-point data by acquiring a fraction part, an exponent part, and a sign of the floating type from the input data, and a floating-point arithmetic logic unit which receives the output of the floating-point converter and calculates the floating-point data. The floating-point converter acquires the exponent part by performing addition and subtraction of the decimal point position data and the shift amount of the fraction part to the integer data.
    • 提供了一种微控制器及其控制系统,其中用于执行浮点运算的程序代码的增加,特别是由于变量引起的代码量的增加被抑制,并且用于转换的处理开销 定点数据进入浮点数据减少。 微控制器包括一个浮点转换器,它将整数数据和对应的小数点位置数据作为定点数据输入,并通过获取浮点数的分数部分,指数部分和符号将输入数据转换为浮点数据 从输入数据输入;以及浮点算术逻辑单元,接收浮点转换器的输出并计算浮点数据。 浮点转换器通过对小数点位置数据和分数部分的移位量进行加,减来获取指数部分到整数数据。