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11. 发明授权

US07639038B2 Terminating resistance adjusting method, semiconductor integrated circuit and semiconductor device 失效
标题翻译：终端电阻调节方法，半导体集成电路和半导体器件
公开(公告)号：US07639038B2
公开(公告)日：2009-12-29
申请号：US11485396
申请日：2006-07-13
申请人： Yutaka Nemoto , Yoshimasa Ogawa , Miki Yanagawa , Makoto Koga
发明人： Yutaka Nemoto , Yoshimasa Ogawa , Miki Yanagawa , Makoto Koga
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0298
摘要： A terminal resistance adjusting method adjusts a terminating resistance within a semiconductor integrated circuit. The method includes obtaining a comparison result by comparing a reference voltage and a voltage of a first node that is coupled to a first voltage via a current supply circuit, the first voltage being one of a power supply voltage and a ground voltage, controlling a monitoring resistor part which has a plurality of first resistors when making a calibration, so as to selectively couple the first resistors in parallel between the first node and a second voltage based on the comparison result, the second voltage being the other of the power supply voltage and the ground voltage, and controlling a terminating resistor part which has a plurality of second resistors when controlling the terminating resistance of the terminating part, so as to selectively couple the second resistors in parallel between a second node and the second voltage based on the comparison result similarly to the first resistors of the monitoring resistor part.
摘要翻译：终端电阻调整方法调整半导体集成电路内的终端电阻。该方法包括通过比较经由电流供应电路耦合到第一电压的第一节点的参考电压和电压，第一电压是电源电压和接地电压之一来获得比较结果，控制监视电阻部分，当进行校准时具有多个第一电阻器，以便基于比较结果选择性地将第一电阻并联在第一节点和第二电压之间，第二电压是电源电压的另一个，接地电压，并且当控制终端部分的终止电阻时控制具有多个第二电阻器的终端电阻器部分，以便基于比较结果选择性地将第二电阻并联连接在第二节点和第二电压之间类似于监控电阻器部分的第一个电阻。

12. 发明授权

US06567286B2 Contents addressable memory with accelerated entry data shunting 有权
公开(公告)号：US06567286B2
公开(公告)日：2003-05-20
申请号：US10043113
申请日：2002-01-14
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G11C1500
CPC分类号： G11C15/04 , G11C15/00
摘要： A contents addressable memory comprises: memory cells arranged in a matrix at positions where word lines extending along a row cross bit lines extending along a column; and search buses extending along the column and match lines extending along the row; and a comparison circuit, provided in each memory cell, comparing data in search bus and data stored in memory cell and outputting comparison result to the match line. Transfer units having a first transfer gate, a transfer cell for temporarily storing data from memory cell, and a second transfer gate are provided between a pair of memory cells arranged along the column. Data from one of pair of memory cells is stored in the transfer cell via first or second transfer gate, then that data stored in transfer cell is stored in other of pair of memory cells via the second or first transfer gate.

13. 发明授权

US06486698B2 LSI device capable of adjusting the output impedance to match the characteristic impedance 失效
公开(公告)号：US06486698B2
公开(公告)日：2002-11-26
申请号：US09759160
申请日：2001-01-16
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： H03K1716
CPC分类号： H03K19/0005 , H03K19/1736
摘要： According to an aspect of the present invention there is provided an LSI device having an output terminal outputting a data, comprising a data output circuit connected to the output terminal and capable of adjusting an output impedance thereof; and an adjustment circuit which detects a transient voltage at the output terminal when an output logic of the data output circuit is switched in a condition that a transmission line not terminated by a terminating resistor is connected to the output terminal, compares the transient voltage with a reference voltage, and adjusts the output impedance of the data output circuit so as to match a characteristic impedance of the transmission line. According to the present invention, as the transient voltage of the output terminal connected to the transmission line is detected, and the output impedance of the data output circuit is adjusted, it is possible to adjust so that output impedance of the data output circuit is matched with characteristic impedance of the transmission line even if manufacture processes, use temperatures, power supply voltages, characteristic impedance of the transmission line, or the like fluctuates or is changed.

14. 发明授权

US08572424B2 Semiconductor device to select and output data to a data bus 有权
标题翻译：半导体器件选择和输出数据到数据总线
公开(公告)号：US08572424B2
公开(公告)日：2013-10-29
申请号：US11806327
申请日：2007-05-31
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G06F13/42
CPC分类号： G11C7/10 , G06F13/4018 , G11C7/1045 , G11C7/1051 , G11C7/106 , H03K5/135 , H03M9/00
摘要： A semiconductor device that can transmit data in wide bus width regardless of the width of an external data bus connected thereto. In a semiconductor device on the data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a time and a data output section outputs these pieces of data to an external data bus of a width of L(=m/n) bits. At this time an output control circuit controls the selection of data by the data selection circuit and a synchronous signal output section outputs a synchronous signal indicative of selected data. In a semiconductor device on the data input side, a data input section accepts data transferred via an external data bus and a data get circuit outputs the data to an internal data bus corresponding to a synchronous signal a synchronous signal input section accepted. By getting data corresponding to all synchronous signals, the data get circuit will get m-bit data.
摘要翻译：无论与其连接的外部数据总线的宽度如何，都可以以宽的总线宽度传输数据。在数据输出侧的半导体器件中，m位内部数据被分成n个块。数据选择电路一次选择m / n条数据，数据输出部分将这些数据输出到宽（L =（m / n））位的外部数据总线。此时，输出控制电路通过数据选择电路控制数据的选择，同步信号输出部输出表示所选数据的同步信号。在数据输入侧的半导体装置中，数据输入部接受通过外部数据总线传送的数据，数据获取电路将数据输出到对应于接受的同步信号输入部的同步信号的内部数据总线。通过获取对应于所有同步信号的数据，数据获取电路将获得m位数据。

15. 发明申请

US20070240009A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070240009A1
公开(公告)日：2007-10-11
申请号：US11806327
申请日：2007-05-31
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G06F13/00
CPC分类号： G11C7/10 , G06F13/4018 , G11C7/1045 , G11C7/1051 , G11C7/106 , H03K5/135 , H03M9/00
摘要： A semiconductor device that can transmit data in wide bus width regardless of the width of an external data bus connected thereto. In a semiconductor device on the data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a time and a data output section outputs these pieces of data to an external data bus of a width of L(=m/n) bits. At this time an output control circuit controls the selection of data by the data selection circuit and a synchronous signal output section outputs a synchronous signal indicative of selected data. In a semiconductor device on the data input side, a data input section accepts data transferred via an external data bus and a data get circuit outputs the data to an internal data bus corresponding to a synchronous signal a synchronous signal input section accepted. By getting data corresponding to all synchronous signals, the data get circuit will get m-bit data.
摘要翻译：无论与其连接的外部数据总线的宽度如何，都可以以宽的总线宽度传输数据。在数据输出侧的半导体器件中，m位内部数据被分成n个块。数据选择电路一次选择m / n条数据，数据输出部分将这些数据输出到宽（L =（m / n））位的外部数据总线。此时，输出控制电路通过数据选择电路控制数据的选择，同步信号输出部输出表示所选数据的同步信号。在数据输入侧的半导体装置中，数据输入部接受通过外部数据总线传送的数据，数据获取电路将数据输出到对应于接受的同步信号输入部的同步信号的内部数据总线。通过获取对应于所有同步信号的数据，数据获取电路将获得m位数据。

16. 发明授权

US06885571B2 Associative memory having a search bus driving circuit for supplying search data to associative memory cells 失效
标题翻译：关联存储器具有用于向关联存储单元提供搜索数据的搜索总线驱动电路
公开(公告)号：US06885571B2
公开(公告)日：2005-04-26
申请号：US10615910
申请日：2003-07-10
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/04 , G11C15/00
摘要： A memory cell matrix with a plurality of associative memory cells and match lines are respectively divided into two in the direction of the match line. A first memory cell matrix is provided with a match line pre-charge circuit that pre-charges the match line in the first memory cell matrix, and a match line sense amplifier that detects the potential of the match line. A second memory cell matrix is provided with a match line pre-charge circuit that pre-charges the match line in the second memory cell matrix, a match line sense amplifier that detects the potential of the match line in the second memory cell matrix, and a second match line control circuit. The second match line control circuit operates the match line pre-charge circuit in the second memory cell matrix, to pre-charge the match line, only when the data comparison result in the first memory cell matrix indicates agreement.
摘要翻译：具有多个关联存储器单元和匹配线的存储单元矩阵分别在匹配线的方向上分成两个。第一存储单元矩阵设置有预充电第一存储单元矩阵中的匹配线的匹配线预充电电路和检测匹配线的电位的匹配线读出放大器。第二存储单元矩阵设置有预充电第二存储单元矩阵中的匹配线的匹配线预充电电路，检测第二存储单元矩阵中匹配线的电位的匹配线读出放大器，以及第二匹配线控制电路。第二匹配线控制电路在第二存储单元矩阵中操作匹配线预充电电路，以仅在第一存储单元矩阵中的数据比较结果指示一致时对该匹配线进行预充电。

17. 发明授权

US06560133B2 Content addressable memory device with advanced precharge timing 有权
公开(公告)号：US06560133B2
公开(公告)日：2003-05-06
申请号：US10066628
申请日：2002-02-06
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A content addressable memory device includes a match line having a potential thereof changed according to whether data of a memory cell matches a search key of a search bus, a precharge circuit which precharges the match line, a sample-&-hold circuit which samples and holds the potential of the match line, and a detection circuit which detects the potential held by the sample-&-hold circuit.

18. 发明授权

US06542392B2 Content addressable memory devices determining entry data priority by valid data length 有权
公开(公告)号：US06542392B2
公开(公告)日：2003-04-01
申请号：US10080559
申请日：2002-02-25
申请人： Miki Yanagawa
发明人： Miki Yanagawa
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A content addressable memory device which determines the top priority entry data without assigning priorities to addresses. If ternary data stored in a cell is invalid data, and other cell at the same bit position stores valid data of entry data identical to an entry key, the entry data is determined not to be a candidate of the top priority entry data. The last entry data which has not determined not to be a candidate is determined to be the top priority data. Compared to the conventional technology which relied on the relationship between a memory address and a priority, the performance of memory system is significantly improved.

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