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11. 发明申请

US20080074502A1 Digital Camera 有权
标题翻译：数码相机
公开(公告)号：US20080074502A1
公开(公告)日：2008-03-27
申请号：US10543056
申请日：2003-12-25
申请人： Yasumasa Nakajima , Shuji Tsuji , Masanobu Shirakawa
发明人： Yasumasa Nakajima , Shuji Tsuji , Masanobu Shirakawa
IPC分类号： H04N5/225
CPC分类号： H04N5/262 , H04N5/772 , H04N5/907 , H04N9/8042
摘要： A digital camera including a layout inputting unit that inputs a layout in drawing a digital image, an internal memory stored with the inputted layout, a selection receiving unit (S400) that receives selection of the layout stored in the internal memory, an object image outputting unit (S410, S420) that outputs the digital image outputted by the converting unit to a removable memory by being related to the layout selected by the selection receiving unit, and a layout unit (S440) that outputs the layout stored in the internal memory in the removable memory stored with the digital image by the object image outputting unit.
摘要翻译：一种数字照相机，包括输入绘制数字图像的布局的布局输入单元，存储有输入布局的内部存储器，接收对存储在内部存储器中的布局的选择的选择接收单元（S 400），对象图像输出单元（S 410，S 420），其通过与由选择接收单元选择的布局相关联将由转换单元输出的数字图像输出到可移动存储器;以及布局单元（S 440），其输出存储在通过对象图像输出单元与数字图像一起存储在可移动存储器中的内部存储器。

12. 发明申请

US20050122412A1 Digital camera 有权
标题翻译：数码相机
公开(公告)号：US20050122412A1
公开(公告)日：2005-06-09
申请号：US10965858
申请日：2004-10-18
申请人： Masanobu Shirakawa , Shuji Tsuji
发明人： Masanobu Shirakawa , Shuji Tsuji
IPC分类号： A61K38/00 , C07K16/28 , C07K16/46 , H04N1/00 , H04N1/21 , H04N1/387 , H04N5/262
CPC分类号： H04N1/3872 , A61K38/00 , C07K2317/24 , C07K2319/00 , H04N1/0035 , H04N1/32101 , H04N1/3871 , H04N5/2621 , H04N2101/00 , H04N2201/3225 , H04N2201/3263 , H04N2201/3277
摘要： There are provided a framing assisting means for displaying as a moving picture object data as well as a profile of an area that is synthesized with a foreground of selected background data on an LCD 26 in a first magnification, a recording means for storing the object data selected by a shutter instruction in a nonvolatile memory to correlate with the selected background data, and a playing means for displaying as a still picture the object data stored in the nonvolatile memory and the background data correlated with the object data on the LCD 26 by applying a magnification varying process that is used to display the object data on the LCD 26 in a magnification smaller than the first magnification.
摘要翻译：提供了一种成帧辅助装置，用于以第一放大率在LCD 26上显示作为运动图像对象数据以及与所选择的背景数据的前景合成的区域的轮廓;存储装置，用于存储对象数据通过非易失性存储器中的快门指令选择与所选择的背景数据相关的播放装置，以及播放装置，用于通过应用在LCD 26上显示存储在非易失存储器中的对象数据和与对象数据相关的背景数据作为静止图像用于以小于第一倍率的倍率在LCD 26上显示对象数据的倍率变化处理。

13. 发明申请

US20130100754A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING DATA THEREOF 有权
标题翻译：非挥发性半导体存储器件及其数据读取方法
公开(公告)号：US20130100754A1
公开(公告)日：2013-04-25
申请号：US13425859
申请日：2012-03-21
申请人： Norichika ASAOKA , Masanobu Shirakawa
发明人： Norichika ASAOKA , Masanobu Shirakawa
IPC分类号： G11C7/00
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3404
摘要： A memory string includes a semiconductor layer, a charge accumulation layer, and a conductive layer. The semiconductor layer extends in a direction perpendicular to the semiconductor substrate and functions as a body of a memory cell. The charge accumulation layer may accumulate charges. The conductive layer sandwiches the charge accumulation layer with the semiconductor layer, and functions as a gate of the memory cell. The control circuit performs, before a read operation, a refresh operation of rendering the selected memory cell and a non-selected memory cell conductive to conduct a current from a first end to a second end of the memory string.
摘要翻译：存储器串包括半导体层，电荷累积层和导电层。半导体层在垂直于半导体衬底的方向上延伸并用作存储单元的主体。电荷累积层可能累积电荷。导电层用半导体层夹杂电荷累积层，起着存储单元的栅极的作用。控制电路在读取操作之前执行渲染所选择的存储单元和非选择存储单元的刷新操作导通以将电流从存储器串的第一端传送到第二端。

14. 发明授权

US08320200B2 Semiconductor storage device and method of reading data therefrom 有权
标题翻译：半导体存储装置及从其读取数据的方法
公开(公告)号：US08320200B2
公开(公告)日：2012-11-27
申请号：US13332469
申请日：2011-12-21
申请人： Toshio Yamamura , Masanobu Shirakawa
发明人： Toshio Yamamura , Masanobu Shirakawa
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C16/26 , G11C2207/2245
摘要： A semiconductor memory device includes a first memory cell array having a first plane which is composed of a plurality of blocks each having a plurality of memory cells, a sense circuit which reads data the memory cells, a sequencer which receives control signals from outside, a first address register, and a second address register which receives an output address from the first address register and outputs an address signal in response to an address control signal from the sequencer. In reading from the memory cells, the sequencer reads a page n in accordance with the address stored in the second address register, then transfers an address stored in the first address register to the second address register concurrently with outputting data read from the page n to outside and reads data from an arbitrary page m in accordance with the address transferred to the second address register.
摘要翻译：半导体存储器件包括具有第一平面的第一存储单元阵列，该第一平面由多个块组成，每个块具有多个存储单元，读取存储单元的数据的读出电路，从外部接收控制信号的定序器，第一地址寄存器和第二地址寄存器，其从第一地址寄存器接收输出地址，并响应于来自定序器的地址控制信号而输出地址信号。在从存储器单元读取时，定序器根据存储在第二地址寄存器中的地址读取页n，然后将存储在第一地址寄存器中的地址同时传送到第二地址寄存器，同时输出从页n读取的数据到根据传送到第二地址寄存器的地址从任意页面m读取数据。

15. 发明授权

US08269837B2 Digital camera and image processing apparatus 有权
标题翻译：数码相机和图像处理装置
公开(公告)号：US08269837B2
公开(公告)日：2012-09-18
申请号：US11003783
申请日：2004-12-06
申请人： Masanobu Shirakawa , Shuji Tsuji
发明人： Masanobu Shirakawa , Shuji Tsuji
IPC分类号： H04N5/228 , H04N5/232 , H04N9/07 , H04N1/21 , H04N1/04 , H04N20/75 , G03B17/18 , G06F3/048
CPC分类号： H04N5/2621 , G06F3/12 , G06K15/02 , H04N1/387 , H04N1/3871 , H04N1/393 , H04N5/225 , H04N5/23293 , H04N5/2628 , H04N5/272 , H04N5/772 , H04N5/907 , H04N9/8047 , H04N9/8205
摘要： Default image data and subject image data are stored separately in nonvolatile memory and when the subject image data stored in the nonvolatile memory is displayed in a standard playback mode, the subject image data is displayed on an LCD at a specific scaling factor (first scaling factor) determined by the image size of the subject image data regardless of whether or not default image data is set for the subject image data. On the other hand, when composite image data is displayed in a print preview mode, scaling processing to display the subject image data on the LCD at a smaller scaling factor than the first scaling factor is performed so that the whole of the composite image data can be displayed on one screen of the display.
摘要翻译：默认图像数据和被摄体图像数据分别存储在非易失性存储器中，并且当以标准重放模式显示存储在非易失性存储器中的被摄体图像数据时，被摄体图像数据以特定缩放因子（第一比例因子），而不管是否为被摄体图像数据设定了默认图像数据。另一方面，当以打印预览模式显示合成图像数据时，执行以比第一缩放因子更小的缩放因子在LCD上显示被摄体图像数据的缩放处理，使得整个合成图像数据可以显示在屏幕的一个屏幕上。

16. 发明授权

US07573601B2 Digital camera 有权
标题翻译：数码相机
公开(公告)号：US07573601B2
公开(公告)日：2009-08-11
申请号：US10965858
申请日：2004-10-18
申请人： Masanobu Shirakawa , Shuji Tsuji
发明人： Masanobu Shirakawa , Shuji Tsuji
IPC分类号： G06F15/00 , G06K15/00 , H04N1/393 , H04N1/46 , H04N7/00 , H04N5/76 , H04N5/262
CPC分类号： H04N1/3872 , A61K38/00 , C07K2317/24 , C07K2319/00 , H04N1/0035 , H04N1/32101 , H04N1/3871 , H04N5/2621 , H04N2101/00 , H04N2201/3225 , H04N2201/3263 , H04N2201/3277
摘要： There are provided a framing assisting means for displaying as a moving picture object data as well as a profile of an area that is synthesized with a foreground of selected background data on an LCD 26 in a first magnification, a recording means for storing the object data selected by a shutter instruction in a nonvolatile memory to correlate with the selected background data, and a playing means for displaying as a still picture the object data stored in the nonvolatile memory and the background data correlated with the object data on the LCD 26 by applying a magnification varying process that is used to display the object data on the LCD 26 in a magnification smaller than the first magnification.
摘要翻译：提供了一种成帧辅助装置，用于以第一放大率在LCD 26上显示作为运动图像对象数据以及与所选择的背景数据的前景合成的区域的轮廓;存储装置，用于存储对象数据通过非易失性存储器中的快门指令选择与所选择的背景数据相关的播放装置，以及播放装置，用于通过应用在LCD 26上显示存储在非易失存储器中的对象数据和与对象数据相关的背景数据作为静止图像用于以小于第一倍率的倍率在LCD 26上显示对象数据的倍率变化处理。

17. 发明申请

US20080246854A1 DIGITAL CAMERA RECORDING A COMPOSITE IMAGE 有权
标题翻译：数码相机记录复合图像
公开(公告)号：US20080246854A1
公开(公告)日：2008-10-09
申请号：US12137759
申请日：2008-06-12
申请人： Shuji TSUJI , Yasumasa Nakajima , Masanobu Shirakawa
发明人： Shuji TSUJI , Yasumasa Nakajima , Masanobu Shirakawa
IPC分类号： H04N5/228
CPC分类号： H04N5/2621 , H04N5/272
摘要： A digital camera capable of recording a subject image so that the subject image can be drawn as it is combined with a selected default image and so that the subject image can be drawn separately from the selected default image. The digital camera includes an image processor which creates subject image data based on output of an image sensor and a default image setting unit which stores subject image data in a removable memory together with information for associating background data with the subject image data, whereby the subject image data, rather than the data provided by combining the subject image data and the background data, is stored in the removable memory and the subject image data and the background data are associated with each other.
摘要翻译：能够记录被摄体图像的数字照相机，使得被摄体图像能够被绘制为与所选择的默认图像组合，并且可以与所选择的默认图像分离地绘制被摄体图像。数字照相机包括：图像处理器，其基于图像传感器的输出创建被摄体图像数据;以及默认图像设置单元，用于将背景数据与对象图像数据相关联的信息与用于将背景数据相关联的主题图像数据存储在可移动存储器中，由此，图像数据而不是通过组合主体图像数据和背景数据提供的数据被存储在可移动存储器中，并且对象图像数据和背景数据彼此相关联。

18. 发明申请

US20050179790A1 Digital camera 审中-公开
标题翻译：数码相机
公开(公告)号：US20050179790A1
公开(公告)日：2005-08-18
申请号：US11045494
申请日：2005-01-31
申请人： Yasumasa Nakajima , Masanobu Shirakawa , Shuji Tsuji
发明人： Yasumasa Nakajima , Masanobu Shirakawa , Shuji Tsuji
IPC分类号： H04N5/222 , H04N5/272 , H04N5/77 , H04N5/907 , H04N9/804
CPC分类号： H04N5/222 , H04N5/272 , H04N5/772 , H04N5/907 , H04N9/8047 , H04N2101/00 , H04N2201/3225 , H04N2201/325 , H04N2201/3277
摘要： Background data to be synthesized with the subject data in which the subject area to which an image represented by the subject data is allocated is previously set in an image represented by the background data, and partial background data associated with the background data, showing at least a part of the area of the image represented by the background data that includes the subject area and having the number of pixels accommodated in a display are stored in a nonvolatile memory. The subject data is synthesized with the partial background data and the synthesized image data is displayed on the display (S230) The subject data is associated with the background data associated with the partial background data and the associated image data is stored in the nonvolatile memory (S260 and S270).
摘要翻译：将被分配了由被摄体数据表示的图像的被摄体区域的对象数据合成的背景数据预先设置在由背景数据表示的图像中，并且与背景数据相关联的部分背景数据至少显示由包括被摄体区域并且具有容纳在显示器中的像素数的背景数据表示的图像的区域的一部分被存储在非易失性存储器中。主体数据与部分背景数据合成，并且合成图像数据被显示在显示器上（S 230）。对象数据与与部分背景数据相关联的背景数据相关联，并且相关联的图像数据被存储在非易失性存储器中（S 260和S 270）。

19. 发明授权

US08570802B2 Nonvolatile semiconductor memory device capable of speeding up write operation 有权
标题翻译：能够加速写入操作的非易失性半导体存储器件
公开(公告)号：US08570802B2
公开(公告)日：2013-10-29
申请号：US13235396
申请日：2011-09-18
申请人： Masanobu Shirakawa
发明人： Masanobu Shirakawa
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3454
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, write circuit, memory unit, and voltage generation unit. A plurality of strings is arranged in the memory cell array, each of which includes a plurality of memory cells connected to word lines. The write circuit selects a first string selected as a sample from the memory cell array, and writes data to the memory cell. The memory unit holds, for each word line, the number of write operations to each memory cell of the first string. When data is written to each memory cell of a second string other than the first string, the voltage generation unit generates an initial write voltage based on the number of write operations, which corresponds to the selected word line and is read out from the memory unit.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元阵列，写入电路，存储单元和电压产生单元。多个串被布置在存储单元阵列中，每个阵列包括连接到字线的多个存储单元。写入电路从存储单元阵列中选择作为样本选择的第一串，并将数据写入存储单元。存储器单元对于每个字线保持对第一字符串的每个存储器单元的写入操作的数量。当将数据写入除第一串之外的第二串的每个存储单元时，电压产生单元基于与所选择的字线相对应的写入操作次数产生初始写入电压，并从存储器单元读出。

20. 发明申请

US20120243309A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120243309A1
公开(公告)日：2012-09-27
申请号：US13419953
申请日：2012-03-14
申请人： Norichika ASAOKA , Masanobu Shirakawa , Kiyotaro Itagaki
发明人： Norichika ASAOKA , Masanobu Shirakawa , Kiyotaro Itagaki
IPC分类号： G11C11/40
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/10 , G11C2213/71 , H01L27/1157 , H01L27/11582
摘要： When performing a data erase operation, the control circuit generates positive holes at least at any one of the drain side select transistor and the source side select transistor, and supply the positive holes to a body of the memory string to raise a voltage of the body of the memory string to a first voltage. Then, it applies a voltage smaller than the first voltage to a first word line among the plurality of the word lines during a first time period. In addition, it applies a voltage smaller than the first voltage to a second word line different from the first word line during a second time period. The second time period is different from the first time period.
摘要翻译：当执行数据擦除操作时，控制电路至少在漏极侧选择晶体管和源极侧选择晶体管中的任何一个处产生正空穴，并且将正空穴提供给存储器体的主体以提高主体的电压的存储器串到第一电压。然后，在第一时间段期间，将多个字线中的第一电压小于第一电压的电压施加到第一字线。此外，在第二时间段期间，它将小于第一电压的电压施加到与第一字线不同的第二字线。第二时间段与第一时间段不同。

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