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11. 发明授权

US06886235B2 Joint device and method of producing its housing 失效
标题翻译：联合装置及其制造方法
公开(公告)号：US06886235B2
公开(公告)日：2005-05-03
申请号：US10398280
申请日：2001-10-17
申请人： Yoshihiro Suzuki , Kouichi Fujita , Yasuhiro Kizaki
发明人： Yoshihiro Suzuki , Kouichi Fujita , Yasuhiro Kizaki
IPC分类号： B21J5/02 , B21K1/14 , B21K1/76 , F16C11/06 , B23P13/04
CPC分类号： F16C11/0623 , B21J5/02 , B21K1/14 , B21K1/762 , F16C11/06 , Y10T29/49996 , Y10T403/32631
摘要： The invention concerns a method of manufacturing a joint housing, in particular for vehicle track rods, having an integral shaft with an internal thread designed to hold a longitudinal pin, the housing being produced from a blank with a ball-like enlargement at one end. In order to ensure low manufacturing costs and low consumption of energy and materials, a longitudinal cavity with a diameter exceeding that of the internal thread and a length exceeding that of the threaded section is first produced in the shaft of the blank by rearwards cup extrusion and the diameter of the threaded section subsequently reduced to that of the thread core while at the same time shaping the surface of the wall to give a flat key face, the overall process being a cold-forming one. Finally, both the external and internal features of the housing are produced by heading, cupping, punching and forming to size perpendicular the to longitudinal axis in the region of the enlargement.
摘要翻译：本发明涉及一种制造接头壳体的方法，特别是用于车辆轨道杆的方法，该方法具有一体的轴，其具有设计成保持纵向销的内螺纹，该壳体由一端具有球状扩大的坯件制成。为了确保低的制造成本和能量和材料的低消耗，首先通过向后杯挤出在坯料的轴中产生直径超过内螺纹并且长度超过螺纹部分的纵向腔，并且螺纹部分的直径随后减小到螺纹芯的直径，同时使壁的表面成形以形成平面的键面，整个过程是冷成形的。最后，壳体的外部和内部特征都是通过在放大的区域中的垂直于纵向轴线的方向，拔罐，冲压和成形来产生的。

12. 发明授权

US5961745A Fe Based soft magnetic glassy alloy 失效
标题翻译：铁基软磁玻璃合金
公开(公告)号：US5961745A
公开(公告)日：1999-10-05
申请号：US832325
申请日：1997-03-26
申请人： Akihisa Inoue , Takao Mizushima , Kouichi Fujita , Oki Yamaguchi , Akihiro Makino
发明人： Akihisa Inoue , Takao Mizushima , Kouichi Fujita , Oki Yamaguchi , Akihiro Makino
IPC分类号： C22C45/02 , H01F1/153
CPC分类号： H01F1/15308
摘要： The present invention is directed to provide a Fe based glassy alloy which exhibits soft magnetic characteristics at room temperature, has a thickness greater than that of a conventional amorphous alloy prepared by a liquid quenching process and can be easily formed in bulk. The Fe based glassy alloy in accordance with the present invention has a temperature distance .DELTA.T.sub.x, expressed by the equation .DELTA.T.sub.x =T.sub.x -T.sub.g, of a supercooled liquid of not less than 35.degree. C., wherein Tx indicates crystallization temperature and Tg represents glass transition temperature.
摘要翻译：本发明旨在提供一种在室温下呈现软磁特性的Fe基玻璃状合金，其厚度大于通过液体淬火工艺制备的常规非晶合金的厚度，并且可以容易地大量地形成。根据本发明的基于Fe的玻璃状合金具有不低于35℃的过冷液体的由等式DELTA Tx = Tx-Tg表示的温度距离DELTA Tx，其中Tx表示结晶温度，Tg表示玻璃化转变温度。

13. 发明授权

US5640598A Data transfer processing system 失效
标题翻译：数据传输处理系统
公开(公告)号：US5640598A
公开(公告)日：1997-06-17
申请号：US595419
申请日：1996-02-05
申请人： Fumiki Sato , Kouichi Fujita
发明人： Fumiki Sato , Kouichi Fujita
IPC分类号： G06F13/28 , G06F9/06 , G06F13/10
CPC分类号： G06F13/28
摘要： A transfer processing procedure comprising instruction words is inputted from an external to a program storing area of a DMA processing unit 40 whose functions are arranged to correspond to instructions, and the DMA processing unit 40 performs a transfer process in accordance with the function corresponding to the inputted instruction word.
摘要翻译：包括指令字的传送处理过程从外部输入到DMA处理单元40的程序存储区域，DMA处理单元40的功能被布置为对应于指令，并且DMA处理单元40根据对应于输入指令字。

14. 发明授权

US5524221A Next instruction pointer calculation system for a microcomputer 失效
标题翻译：下一个微机指令指针计算系统
公开(公告)号：US5524221A
公开(公告)日：1996-06-04
申请号：US311833
申请日：1994-09-23
申请人： Fumiki Sato , Kouichi Fujita
发明人： Fumiki Sato , Kouichi Fujita
IPC分类号： G06F9/22 , G06F9/26 , G06F9/28 , G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/226 , G06F9/321 , G06F9/3802
摘要： A microcomputer comprising an internal decoder for addressing instruction codes in an instruction prefetch buffer, a words field provided preferably in a micro ROM for storing number of words which indicate lengths of various instructions, and position calculating means provided in the bus interface unit for inputting the number of words to indicate an address of instruction code in the instruction prefetch buffer, so that the instruction code is read out concurrently with the execution of the micro instruction.
摘要翻译：一种微型计算机，包括用于寻址指令预取缓冲器中的指令代码的内部解码器，优选地在微ROM中提供的字段，用于存储指示各种指令的长度的字数;以及位置计算装置，设置在总线接口单元中，用于输入指示指令预取缓冲器中的指令代码的地址的字数，使得指令代码与微指令的执行同时读出。

15. 发明授权

US5483477A Multiplying circuit and microcomputer including the same 失效
标题翻译：乘法电路和微机包括相同
公开(公告)号：US5483477A
公开(公告)日：1996-01-09
申请号：US205457
申请日：1994-03-04
申请人： Fumiki Sato , Kouichi Fujita
发明人： Fumiki Sato , Kouichi Fujita
IPC分类号： G06F7/49 , G06F7/48 , G06F7/52 , G06F7/533 , G06F7/00 , G06F15/00
CPC分类号： G06F7/5338 , G06F7/4824
摘要： A multiplying circuit wherein an adder 7 outputs a value "0" in which both of a positive part and a negative part of a number with a redundant code are "1", and at a last cycle of the multiplication cycles, the finish detecting circuit 13 detects finishing of multiplication cycles by detecting that "1" exists in a portion storing a positive part of a number with a redundant code of the third bit from the lowest bit of the second latch 8 and in a portion storing a negative part of the same at the same time. In such a construction, a counter circuit for counting multiplication cycles according to the Booth algorithm utilizing a number with a redundant code can be omitted. Accordingly, the number of transistors is reduced and the circuit configuration becomes simple.
摘要翻译：乘法电路，其中加法器7输出其中具有冗余代码的数字的正部分和负部分都为“1”的值“0”，并且在乘法周期的最后一个周期，完成检测电路 13检测乘法周期的完成，通过检测在存储来自第二锁存器8的最低位的第三位的冗余代码的数字的正部分中存储的部分中存在“1”，并且存储负同一时间。在这种结构中，可以省略利用具有冗余码的数量的根据布斯算法进行乘法周期计数的计数器电路。因此，晶体管的数量减少，电路结构变得简单。

16. 发明授权

US4651113A Amplitude stabilized crystal oscillator 失效
标题翻译：振幅稳定的晶体振荡器
公开(公告)号：US4651113A
公开(公告)日：1987-03-17
申请号：US842353
申请日：1986-03-18
申请人： Kouichi Fujita
发明人： Kouichi Fujita
IPC分类号： H03F1/34 , H03B5/36 , H03L5/00
CPC分类号： H03B5/364 , H03L5/00
摘要： An oscillator circuit in a semiconductor substrate of an integrated circuit, includes a gain correction circuit portion connected between the output terminal of the feedback circuit portion and the input end of the amplifier circuit portion composed of MOS transistors. The gain correction circuit portion suppresses the excessive amplitude of the output signal of the feedback circuit portion, so that the characteristic of the waveform of the output signal of the oscillator device is improved.
摘要翻译：集成电路的半导体衬底中的振荡电路包括连接在反馈电路部分的输出端和由MOS晶体管组成的放大器电路部分的输入端之间的增益校正电路部分。增益校正电路部分抑制反馈电路部分的输出信号的过大振幅，从而提高振荡器装置的输出信号的波形特性。

17. 发明授权

US5926037A Buffer circuit which transfers data held in a first latch circuit to a second latch circuit 失效
标题翻译：将保持在第一锁存电路中的数据传送到第二锁存电路的缓冲电路
公开(公告)号：US5926037A
公开(公告)日：1999-07-20
申请号：US890619
申请日：1997-07-09
申请人： Fumiki Sato , Kouichi Fujita
发明人： Fumiki Sato , Kouichi Fujita
IPC分类号： G11C11/417 , G11C19/00 , H03K3/037 , H03K3/356 , H03K19/0175 , G11C7/00 , H03K19/094
CPC分类号： H03K3/356191
摘要： A buffer circuit which can solve a problem of a conventional buffer circuit in that high speed data transfer is hindered because of parasitic capacitance of signal lines, which has an affect on the discharge time of inverters in a latch circuit of the buffer circuit, when the buffer circuit changes its state from a first term (non-transfer mode) to a second term (transfer mode). The buffer circuit solves this problem by pouring a current, which flows thereinto from a first signal line, into ground through a first PMOS transistor, a first NMOS transistor and a third NMOS transistor, and by pouring a current, which flows thereinto from a second signal line, into the ground through a second PMOS transistor, a second NMOS transistor and the third NMOS transistor.
摘要翻译：由于在对缓冲电路的锁存电路中的反相器的放电时间产生影响的信号线的寄生电容的情况下，可以解决在该高速数据传输中解决现有的缓冲电路的问题的缓冲电路，缓冲电路将其状态从第一项（非转移模式）改变为第二项（传输模式）。缓冲电路通过将从第一信号线流入的电流通过第一PMOS晶体管，第一NMOS晶体管和第三NMOS晶体管注入接地来解决这个问题，并且通过从第二PMOS晶体管，第一NMOS晶体管和第三NMOS晶体管中流入的电流信号线通过第二PMOS晶体管，第二NMOS晶体管和第三NMOS晶体管插入地。

18. 发明授权

US5479632A Microcomputer having two-level memory to facilitate calculation of effective addresses 失效
标题翻译：微电脑具有两级存储器，便于计算有效地址
公开(公告)号：US5479632A
公开(公告)日：1995-12-26
申请号：US248833
申请日：1994-05-25
申请人： Fumiki Sato , Kouichi Fujita
发明人： Fumiki Sato , Kouichi Fujita
IPC分类号： G06F9/35 , G06F9/22 , G06F9/30 , G06F12/02 , G06F15/78 , G06F12/08
CPC分类号： G06F9/223 , G06F9/30149
摘要： A microcomputer includes a layered memory having a higher layer for storing a series of instructions forming a program to be executed by the microcomputer and a lower layer, having an upside layer accessed by ID information in the instructions stored in the higher layer memory, and a downside layer, accessed by the upside layer, having a sequence of storage locations storing code data for controlling the execution unit to calculate effective addresses.
摘要翻译：微型计算机包括具有更高层的分层存储器，用于存储形成由微计算机执行的程序的一系列指令和具有通过存储在较高层存储器中的指令中的ID信息访问的上层的下层，以及下侧层，由上侧层访问，具有存储代码数据的一系列存储位置，用于控制执行单元计算有效地址。

19. 发明授权

US5442801A Arithmetic and logic unit 失效
标题翻译：算术逻辑单元
公开(公告)号：US5442801A
公开(公告)日：1995-08-15
申请号：US147269
申请日：1993-11-05
申请人： Fumiki Sato , Kouichi Fujita
发明人： Fumiki Sato , Kouichi Fujita
IPC分类号： G06F7/505 , G06F7/575 , G06F7/38
CPC分类号： G06F7/575
摘要： An arithmetic and logic unit is provided with a first NAND gate (29) which outputs a NAND logic operation result between a first operand (A.sub.i), a second operand (B.sub.i) and a first control signal (S.sub.0), a first EXOR gate (30) which outputs an EXOR logic operation result between the output of the first NAND gate (29) and a second control signal (S.sub.1), an OR gate (31) which outputs an OR logic operation result between the first operand (A.sub.i) and the second operand (B.sub.i), a second NAND gate (32) which outputs a NAND logic operation result between the output of the first EXOR gate (30) and the output of the OR gate (31), a third NAND gate (20) which outputs a NAND logic operation result between a third control signal (S.sub.2) and a carry input (CY.sub.i-1), and a second EXOR gate (21) which outputs an EXOR logic operation result between the output of the second NAND gate (32) and the output of the third NAND gate (20), so that OR, EXOR and AND logic operations and ADD arithmetic operation for the both operands (A.sub.i and B.sub.i) are executed.
摘要翻译：算术和逻辑单元设置有第一NAND门（29），其输出第一操作数（Ai），第二操作数（B 1）和第一控制信号（S 0）之间的与非逻辑运算结果，第一异或门（ 30），其输出第一与非门（29）的输出和第二控制信号（S1）之间的EXOR逻辑运算结果;或门（31），其输出第一操作数（Ai）与第第二操作数（Bi），在第一EXOR门（30）的输出与或门（31）的输出之间输出NAND逻辑运算结果的第二NAND门（32），第三NAND门（20）其输出第三控制信号（S2）和进位输入（CYi-1）之间的NAND逻辑运算结果;以及第二异或门（21），其在第二与非门（32）的输出之间输出EXOR逻辑运算结果）和第三与非门（20）的输出，使得OR，EXOR和AND逻辑运算和ADD算术运算为两个运算（Ai和Bi）。

20. 发明授权

US5423012A Apparatus and method in a computer for executing calculation instructions and data instructions having uniform word lengths 失效
标题翻译：一种用于执行具有均匀字长的计算指令和数据指令的计算机中的装置和方法
公开(公告)号：US5423012A
公开(公告)日：1995-06-06
申请号：US977947
申请日：1992-11-18
申请人： Fumiki Sato , Kouichi Fujita
发明人： Fumiki Sato , Kouichi Fujita
IPC分类号： G06F9/305 , G06F9/30 , G06F9/38 , G06F9/00 , G06F13/00
CPC分类号： G06F9/3814 , G06F9/30145 , G06F9/30167 , G06F9/3802
摘要： In a microcomputer, for using all the instruction words having uniform word length, a first or second instruction word stored in a memory area of a memory indicated by an address of an address register is read in a predetermined word position of an instruction first-reading buffer indicated by a first pointer and the first or second instruction word read from a word position of the instruction first-reading buffer indicated by a second pointer is read in an instruction interpreting section through a second shifter. This instruction interpreting section interprets an instruction word from a bus interface section. In the case of the second instruction word (data instruction), data necessary for a calculation are produced on the basis of data of the second instruction word such as immediate data and offset data. In the case of the first instruction word, a calculation is effected on the basis of data produced by a data expansion section.
摘要翻译：在微型计算机中，为了使用具有均匀字长的所有指令字，存储在由地址寄存器的地址指示的存储器的存储区域中的第一或第二指令字被读入指令第一读取的预定字位置通过第二移位器在指令解释部分中读取由第一指针指示的缓冲器和从第二指针指示的指令第一读取缓冲器的字位置读取的第一或第二指令字。该指令解释部分解释来自总线接口部分的指令字。在第二指令字（数据指令）的情况下，基于诸如立即数据和偏移数据的第二指令字的数据产生计算所需的数据。在第一指令字的情况下，基于由数据扩展部产生的数据进行计算。

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