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11. 发明授权

US6017802A Ultra-short transistor fabrication scheme for enhanced reliability 有权
标题翻译：超短晶体管制造方案，提高可靠性
公开(公告)号：US6017802A
公开(公告)日：2000-01-25
申请号：US176605
申请日：1998-10-21
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/823425 , H01L21/823468 , H01L29/6656 , H01L29/7835 , Y10S257/90
摘要： A detached drain transistor including a semiconductor substrate, a gate dielectric formed on an upper surface of the substrate, a conductive gate formed on the gate dielectric, a first pair of spacer structures, a first source impurity distribution, a second air of spacer structures, and a drain impurity distribution. The conductive gate is laterally disposed over a channel region of the semiconductor substrate. The channel region extends laterally between a first source region of the semiconductor substrate and a detached drain region of the semiconductor substrate. A channel boundary of the detached region is laterally displaced from a first sidewall of the conductive gate by a drain displacement. A channel boundary of the first source region is laterally displaced from a second sidewall of the conductive gate by a source displacement. The first pair of spacer structures is formed in contact with the first and second sidewalls of the conductive gate. A lateral dimension of the first pair of spacer structures is approximately equal to the source displacement. The second pair of spacer structures is formed on exterior sidewalls of the first pair of spacer structures such that exterior sidewalls of the second pair of spacer structures are displaced from respective sidewalls of the conductive gate by approximately said drain displacement. In a presently preferred embodiment, the source displacement is approximately 50 to 400 angstroms while the drain displacement is approximately 500 to 1500 angstroms.
摘要翻译：分离的漏极晶体管，包括半导体衬底，形成在衬底的上表面上的栅极电介质，形成在栅极电介质上的导电栅极，第一对间隔结构，第一源杂质分布，间隔结构的第二空气，和漏极杂质分布。导电栅极横向设置在半导体衬底的沟道区域上方。沟道区域横向延伸在半导体衬底的第一源极区域和半导体衬底的分离的漏极区域之间。分离区域的通道边界通过排水位移从导电浇口的第一侧壁横向移位。第一源极区的沟道边界通过源极位移从导电栅极的第二侧壁横向移位。第一对间隔结构形成为与导电栅极的第一和第二侧壁接触。第一对间隔结构的横向尺寸近似等于源位移。第二对间隔结构形成在第一对间隔结构的外侧壁上，使得第二对间隔结构的外侧壁通过大致所述排水位移从导电栅极的相应侧壁位移。在当前优选的实施例中，源位移为大约50至400埃，而排水位移为约500至1500埃。

12. 发明授权

US5998288A Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate 失效
标题翻译：在衬底上表面凹陷的栅极导体的横向附近形成超薄间隔物
公开(公告)号：US5998288A
公开(公告)日：1999-12-07
申请号：US62095
申请日：1998-04-17
申请人： Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/336 , H01L29/78 , H01L21/3205
CPC分类号： H01L29/66621 , H01L29/665 , H01L29/7834
摘要： An integrated circuit fabrication process is provided for forming relatively thin sidewall spacers extending laterally from upper portions of opposed sidewall surfaces of a transistor gate conductor which resides partially within a trench of a semiconductor substrate. The present invention contemplates etching a trench through a masking layer and partially through a silicon-based substrate arranged underneath the masking layer. A gate dielectric is then formed upon silicon-based surfaces which border the trench. A conformal dielectric layer is deposited across the masking layer and the gate dielectric, followed by the deposition of a gate conductor material across the dielectric layer. The gate conductor material and the dielectric layer are removed from above the upper surface of the masking layer. Portions of the dielectric layer interposed between the masking layer and the gate conductor are etched to a level commensurate with the substrate surface. An LDD implant self-aligned to the lateral boundaries of the masking layer and the gate conductor sidewall surfaces is forwarded into the substrate underneath the trench. Relatively thin oxide spacer structures are then thermally grown upon the sidewall surfaces of the gate conductor. After removing the masking layer, a source/drain implant is performed. In another embodiment, the gate conductor is formed between the opposed lateral boundaries of the masking layer upon the gate dielectric. A source/drain implant is performed after removing the masking. Relatively thin dielectric spacers are formed upon the upper portions of the sidewall surfaces of the gate conductor by depositing and anisotropically etching a dielectric.
摘要翻译：提供了集成电路制造工艺，用于形成相对薄的侧壁间隔件，其侧向地从位于半导体衬底的沟槽内的晶体管栅极导体的相对的侧壁表面的上部横向延伸。本发明考虑通过掩模层蚀刻沟槽，并部分地穿过布置在掩模层下方的硅基衬底。然后在与沟槽接合的硅基表面上形成栅极电介质。在掩模层和栅极电介质之间沉积保形介电层，随后在电介质层上沉积栅极导体材料。栅极导体材料和电介质层从掩蔽层的上表面上方去除。插入在掩模层和栅极导体之间的电介质层的部分被蚀刻到与衬底表面相当的水平。与屏蔽层和栅极导体侧壁表面的横向边界自对准的LDD注入被转移到沟槽下方的衬底中。然后将相对薄的氧化物间隔物结构热生长在栅极导体的侧壁表面上。在去除掩模层之后，执行源极/漏极注入。在另一个实施例中，栅极导体形成在栅极电介质上的掩蔽层的相对的横向边界之间。在去除掩模之后执行源极/漏极注入。通过沉积和各向异性蚀刻电介质，在栅极导体的侧壁表面的上部形成相对薄的电介质间隔物。

13. 发明授权

US5981368A Enhanced shallow junction design by polysilicon line width reduction using oxidation with integrated spacer formation 失效
标题翻译：通过使用集成间隔物形成的氧化，通过多晶硅线宽减小的增强的浅结设计
公开(公告)号：US5981368A
公开(公告)日：1999-11-09
申请号：US187027
申请日：1998-11-05
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/49
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28105 , H01L21/28123 , H01L29/4966
摘要： A method of forming a transistor includes forming a gate dielectric layer upon a substrate, forming a polysilicon layer upon the gate dielectric layer and then forming a thin nitride layer upon the gate polysilicon layer. The thin nitride layer is then pattern etched to define a nitride cap above a future channel. The gate polysilicon layer and a portion of the silicon substrate below the gate dielectric layer is then doped with arsenic. An optional annealing step then causes some of the arsenic to migrate below the nitride cap. A subsequent oxidation step then causes gate conductor/gate oxide stacks with integrated spacers to be defined below the nitride cap. The oxidation step and optional prior annealing step also cause some arsenic to migrate into the channel to form the LDD regions. The substrate is etched to remove portions of the gate polysilicon layer unprotected by the nitride cap. The remaining gate structures below the nitride cap include spacers and LDD regions are formed about the polysilicon gate conductor with the combined structure having a width of the nitride cap. Accordingly, the channel width has been decreased to a size that is even smaller than the width of the nitride cap.
摘要翻译：形成晶体管的方法包括在衬底上形成栅极电介质层，在栅极介电层上形成多晶硅层，然后在栅极多晶硅层上形成薄的氮化物层。然后对薄氮化物层进行图案蚀刻以在未来通道之上限定氮化物帽。栅极多晶硅层和栅极电介质层下面的硅衬底的一部分然后掺杂砷。任选的退火步骤然后使一些砷迁移到氮化物盖下方。随后的氧化步骤然后使得具有集成间隔物的栅极导体/栅极氧化物堆叠被限定在氮化物盖的下方。氧化步骤和可选的先前退火步骤还使一些砷迁移到通道中以形成LDD区域。蚀刻衬底以除去未被氮化物帽保护的栅极多晶硅层的部分。在氮化物盖下面的剩余栅极结构包括间隔物，并且LDD区围绕多晶硅栅极导体形成，其组合结构具有氮化物盖的宽度。因此，通道宽度已经减小到比氮化物盖的宽度更小的尺寸。

14. 发明授权

US5970354A Poly recessed fabrication method for defining high performance MOSFETS 失效
标题翻译：用于定义高性能MOSFET的多凹陷制造方法
公开(公告)号：US5970354A
公开(公告)日：1999-10-19
申请号：US987117
申请日：1997-12-08
申请人： Fred N. Hause , Mark I. Gardner , H. Jim Fulford, Jr.
发明人： Fred N. Hause , Mark I. Gardner , H. Jim Fulford, Jr.
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/66583 , H01L21/28123
摘要： A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers. The method includes forming a plurality of layers including a dielectric layer, a polysilicon layer and a masking layer. An opening is preferably formed in the masking layer, the opening defining the location of the gate conductor. The width of the opening may be narrowed by the use of spacers. A portion of the polysilicon layer defined by the opening is implanted with an n-type impurity. An oxide layer is formed over the implanted portion of the polysilicon layer. The polysilicon layer is etched such that a gate conductor is formed underneath the oxide layer. LDD areas and source/drain areas are subsequently formed adjacent to the gate conductor.
摘要翻译：提出了一种通过使用多晶硅层上面的掩模层来形成栅极导体的方法，以限定栅极的长度。栅极的长度可以通过使用间隔物来调节。该方法包括形成包括电介质层，多晶硅层和掩模层的多个层。优选地，在掩模层中形成开口，该开口限定栅极导体的位置。开口的宽度可以通过使用间隔物变窄。由开口限定的多晶硅层的一部分注入n型杂质。在多晶硅层的注入部分上形成氧化物层。蚀刻多晶硅层，使得在氧化物层下方形成栅极导体。随后在栅极导体附近形成LDD区域和源极/漏极区域。

15. 发明授权

US5962894A Trench transistor with metal spacers 失效
标题翻译：沟槽晶体管与金属间隔
公开(公告)号：US5962894A
公开(公告)日：1999-10-05
申请号：US30052
申请日：1998-02-24
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/417 , H01L29/423 , H01L29/76 , H01L31/062
CPC分类号： H01L29/41775 , H01L29/66621 , H01L29/78
摘要： An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, depositing a blanket layer of conductive metal over the substrate and applying an anisotropic etch to form the metal spacers, depositing a continuous insulative layer over the substrate to provide the gate insulator and the protective insulators, depositing a blanket layer of gate electrode material over the substrate, and polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate. Advantageously, the channel length is significantly smaller than the trench length, and the metal spacers reduce the parasitic resistance of lightly doped source and drain regions.
摘要翻译：公开了具有沟槽中的栅电极和金属间隔物的IGFET。 IGFET包括具有相对的侧壁和半导体衬底中的底表面的沟槽，与侧壁和底表面相邻的金属间隔物，位于金属间隔物之间的底表面上的栅极绝缘体，金属间隔物上的保护绝缘体，栅电极在栅极绝缘体和保护绝缘体上，以及与底表面相邻的源极和漏极。形成IGFET的方法包括将掺杂层注入到衬底中，完全通过掺杂层蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分裂成源极和漏极区域，施加高温退火以扩散在底表面下方的源极和漏极区域，在衬底上沉积导电金属的覆盖层，并施加各向异性蚀刻以形成金属间隔物，在衬底上沉积连续的绝缘层以提供栅极绝缘体和保护绝缘体，覆盖衬底上的栅电极材料层，并且对栅电极材料进行抛光，使得栅电极基本上与衬底的顶表面对准。有利地，沟道长度显着小于沟槽长度，并且金属间隔物减少了轻掺杂源极和漏极区域的寄生电阻。

16. 发明授权

US5946579A Stacked mask integration technique for advanced CMOS transistor formation 失效
标题翻译：叠层掩模集成技术，用于先进的CMOS晶体管形成
公开(公告)号：US5946579A
公开(公告)日：1999-08-31
申请号：US987277
申请日：1997-12-09
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Fred N. Hause
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Fred N. Hause
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336
CPC分类号： H01L29/66583 , H01L21/28052 , H01L21/28123 , H01L21/32137
摘要： A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers. The method includes forming a plurality of layers including a dielectric layer, a polysilicon layer and a masking layer. An opening is preferably formed in the masking layer, the opening defining the location of the gate conductor. The width of the opening may be narrowed by the use of spacers. A portion of the polysilicon layer defined by the opening is implanted with an n-type impurity. A silicide layer is formed upon the upper surface of the exposed polysilicon layer. An oxide layer is formed over the silicide layer. The polysilicon layer is etched such that a gate conductor is formed underneath the oxide layer. LDD areas and source/drain areas are subsequently formed adjacent to the gate conductor.
摘要翻译：提出了一种通过使用多晶硅层上面的掩模层来形成栅极导体的方法，以限定栅极的长度。栅极的长度可以通过使用间隔物来调节。该方法包括形成包括电介质层，多晶硅层和掩模层的多个层。优选地，在掩模层中形成开口，该开口限定栅极导体的位置。开口的宽度可以通过使用间隔物变窄。由开口限定的多晶硅层的一部分注入n型杂质。在暴露的多晶硅层的上表面上形成硅化物层。在硅化物层上形成氧化物层。蚀刻多晶硅层，使得在氧化物层下方形成栅极导体。随后在栅极导体附近形成LDD区域和源极/漏极区域。

17. 发明授权

US5930634A Method of making an IGFET with a multilevel gate 失效
标题翻译：制造具有多级门的IGFET的方法
公开(公告)号：US5930634A
公开(公告)日：1999-07-27
申请号：US844927
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/28035 , H01L21/28052 , H01L29/42376 , H01L29/4925 , H01L29/6659 , H01L29/7833
摘要： A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region. Advantageously, the first photoresist layer can be ultra-thin to enhance the accuracy in which the image pattern is replicated, thereby reducing variations in channel length and device performance.
摘要翻译：公开了一种制造具有包括上下栅极电平的多电平栅极的IGFET的方法。该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上形成厚度至多为1000埃的第一栅极材料，形成第一光致抗蚀剂层第一栅极材料，用第一图案图案照射第一光致抗蚀剂层，并去除第一光致抗蚀剂层的照射部分以在有源区上方提供开口，使用第一光致抗蚀剂层蚀刻通过第一光致抗蚀剂层中的开口的第一栅极材料作为用于形成下栅极电平的第一栅极材料的一部分的蚀刻掩模，去除第一光致抗蚀剂层，在去除第一光致抗蚀剂层之后在下栅极电平上形成上栅极电平，并在其中形成源极和漏极活跃区域。有利地，第一光致抗蚀剂层可以是超薄的，以提高复制图像图案的精度，从而减少通道长度和器件性能的变化。

18. 发明授权

US5904517A Ultra thin high K spacer material for use in transistor fabrication 失效
标题翻译：用于晶体管制造的超薄高K隔离材料
公开(公告)号：US5904517A
公开(公告)日：1999-05-18
申请号：US112529
申请日：1998-07-08
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Derrick J. Wristers
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Derrick J. Wristers
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/49 , H01L21/70
CPC分类号： H01L29/6659 , H01L21/823468 , H01L29/4983 , H01L29/665
摘要： A fabrication process and integrated circuit formed thereby are provided in which relatively thin sidewall spacers extend laterally from opposed sidewall surfaces of a transistor gate conductor. The present invention contemplates forming a gate structure upon a semiconductor substrate. Lightly doped drain impurity areas may be formed in the semiconductor substrate aligned with sidewall of the gate structure. An oxygen-containing dielectric layer is deposited upon the semiconductor topography, followed by deposition of an oxidizable metal upon the dielectric layer. The oxygen-containing dielectric and the oxidizable metal are thermally annealed such that metal oxide spacers are formed adjacent sidewall surfaces of the gate structure. In an embodiment, portions of the dielectric and the metal are selectively removed prior to the anneal. In an alternate embodiment, the metal and the dielectric are annealed first, followed by selective removal of portions of the resulting metal oxide. Following spacer formation, source and drain impurity areas may be formed in the semiconductor substrate aligned with sidewall surfaces of the spacers. A metal silicide may be formed upon upper surfaces of the gate conductor and the source and drain impurity areas.
摘要翻译：提供了由此形成的制造工艺和集成电路，其中较薄的侧壁间隔件从晶体管栅极导体的相对的侧壁表面横向延伸。本发明考虑在半导体衬底上形成栅极结构。可以在与栅极结构的侧壁对准的半导体衬底中形成轻掺杂的漏极杂质区域。在半导体形貌上沉积含氧介电层，然后在电介质层上沉积可氧化金属。含氧电介质和可氧化金属被热退火，使得邻近栅极结构的侧壁表面形成金属氧化物间隔物。在一个实施例中，电介质和金属的部分在退火之前被选择性地去除。在替代实施例中，首先对金属和电介质进行退火，然后选择性地去除所得到的金属氧化物的一部分。在间隔物形成之后，源极和漏极杂质区域可以形成在与间隔物的侧壁表面对准的半导体衬底中。可以在栅极导体的上表面和源极和漏极杂质区域上形成金属硅化物。

19. 发明授权

US5877058A Method of forming an insulated-gate field-effect transistor with metal spacers 失效
标题翻译：用金属间隔物形成绝缘栅场效应晶体管的方法
公开(公告)号：US5877058A
公开(公告)日：1999-03-02
申请号：US703272
申请日：1996-08-26
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/6659 , H01L29/6656
摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.
摘要翻译：公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。金属间隔物还可以提供低电阻漏极和源极触点。

20. 发明授权

US5847428A Integrated circuit gate conductor which uses layered spacers to produce a graded junction 失效
标题翻译：集成电路栅极导体，其使用分层间隔物来产生分级结
公开(公告)号：US5847428A
公开(公告)日：1998-12-08
申请号：US761132
申请日：1996-12-06
申请人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Mark I. Gardner , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/6656 , H01L29/7833 , Y10S257/90
摘要： A transistor is provided with a graded source/drain junction. At least two dielectric spacers are formed in sequence upon the gate conductor. Adjacent dielectric spacers have dissimilar etch characteristics. An ion implant follows the formation of at least two of the dielectric spacers to introduce dopants into the source/drain region of the transistor. The ion implants are placed in different positions a spaced distance from the gate conductor according to a thickness of the dielectric spacers. As the implants are introduced further from the channel, the implant dosage and energy is increased. In a second embodiment, the ion implants are performed in reverse order. The dielectric spacers pre-exist on the sidewall surfaces of the gate conductor. The spacers are sequentially removed followed by an ion implant. An etchant is used which attacks the spacer to be removed but not the spacer beneath to the one being removed. Each time, the implants are performed with a lower energy and with a lower dosage so as to grade the junction with lighter concentrations and energies as the implant areas approach the channel. Reversing the implantation process enables high-temperature thermal anneals required for high-concentration low-diffusivity dopants to be performed first. The LDD implant comprises dopants of lower concentration and higher diffusivity requiring lower temperature anneals. Performing lower temperature anneals later in the sequence affords a lessened opportunity for undesirable short-channel effects.
摘要翻译：晶体管具有渐变源极/漏极结。在栅极导体上依次形成至少两个电介质间隔物。相邻的电介质间隔物具有不同的蚀刻特性。离子注入沿着至少两个电介质间隔物的形成，以将掺杂剂引入到晶体管的源极/漏极区域中。离子植入物根据电介质间隔物的厚度被放置在与栅极导体间隔距离的不同位置。随着植入物从通道进一步引入，植入物剂量和能量增加。在第二实施例中，以相反的顺序执行离子注入。电介质垫片预先存在于栅极导体的侧壁表面上。依次移除间隔物，然后离子注入。使用蚀刻剂来攻击待移除的间隔物，而不是将垫片下移到被去除的间隔物。每次，植入物以较低的能量和较低的剂量进行，以便随着植入区域接近通道而将结点分级为较轻的浓度和能量。倒置注入工艺可以实现高浓度低扩散性掺杂剂首先要求的高温热退火。 LDD植入物包含较低浓度和较高扩散系数的掺杂剂，需要较低的温度退火。在该顺序的稍后进行较低的温度退火可以减少不期望的短通道效应的机会。

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