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    • 12. 发明申请
    • DMA Address Translation in an IOMMU
    • DMA地址转换在IOMMU
    • US20100095085A1
    • 2010-04-15
    • US12635385
    • 2009-12-10
    • Mark D. HummelGeoffrey S. StronginMitchell AlsupMichael HaertelAndrew W. Lueck
    • Mark D. HummelGeoffrey S. StronginMitchell AlsupMichael HaertelAndrew W. Lueck
    • G06F12/10G06F12/00G06F3/00
    • G06F12/1081
    • In an embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory configured to store translation data; and control logic coupled to the memory and configured to translate an I/O device-generated memory request using the translation data. The translation data corresponds to one or more device table entries in a device table stored in a memory system of a computer system that includes the IOMMU, wherein the device table entry for a given request is selected by an identifier corresponding to the I/O device that generates the request. The translation data further corresponds to one or more I/O page tables, wherein the selected device table entry for the given request includes a pointer to a set of I/O page tables to be used to translate the given request.
    • 在一个实施例中,输入/输出(I / O)存储器管理单元(IOMMU)包括被配置为存储转换数据的至少一个存储器; 以及控制逻辑,其耦合到所述存储器并且被配置为使用所述翻译数据来转换I / O设备生成的存储器请求。 翻译数据对应于存储在包括IOMMU的计算机系统的存储器系统中的设备表中的一个或多个设备表条目,其中给定请求的设备表条目由对应于I / O设备的标识符选择 生成请求。 翻译数据还对应于一个或多个I / O页表,其中用于给定请求的所选择的设备表条目包括指向要用于转换给定请求的一组I / O页表的指针。
    • 19. 发明授权
    • System and method for handling device accesses to a memory providing increased memory access security
    • 用于处理对存储器的设备访问的系统和方法,其提供增加的存储器访问安全性
    • US07426644B1
    • 2008-09-16
    • US10011151
    • 2001-12-05
    • Geoffrey S. StronginBrian C. BarnesRodney W. Schmidt
    • Geoffrey S. StronginBrian C. BarnesRodney W. Schmidt
    • G06F21/00G06F21/22
    • G06F12/1441G06F12/1491
    • A host bridge is described including a memory controller and a security check unit. The memory controller is adapted for coupling to a memory storing data arranged within a multiple memory pages. The memory controller receives memory access signals (e.g., during a memory access), and responds to the memory access signals by accessing the memory. The security check unit receives the memory access signals, wherein the memory access signals convey a physical address within a target memory page. The security check unit uses the physical address to access one or more security attribute data structures located in the memory to obtain a security attribute of the target memory page. The security check unit provides the memory access signals to the memory controller dependent upon the security attribute of the target memory page. A computer system is described including a memory storing data arranged within a multiple memory pages, a device operably coupled to the memory and configurable to produce memory access signals, the above described host bridge. The computer system may have, for example, a central processing unit (CPU) including a memory management unit (MMU) operably coupled to the memory and configured to manage the memory. The memory management unit (MMU) may manage the memory such that the memory stores the data arranged within the multiple memory pages. A method is disclosed for providing access security for a memory used to store data arranged within a multiple memory pages.
    • 描述了主桥,包括存储器控制器和安全检查单元。 存储器控制器适于耦合到存储多个存储器页中布置的数据的存储器。 存储器控制器接收存储器访问信号(例如,在存储器访问期间),并且通过访问存储器来响应存储器访问信号。 安全检查单元接收存储器访问信号,其中存储器访问信号传达目标存储器页面内的物理地址。 安全检查单元使用物理地址访问位于存储器中的一个或多个安全属性数据结构,以获得目标存储器页面的安全属性。 安全检查单元根据目标存储器页面的安全属性向存储器控制器提供存储器访问信号。 描述了一种计算机系统,包括存储布置在多个存储器页内的数据的存储器,可操作地耦合到存储器并且可配置为产生存储器访问信号的设备,上述主机桥。 计算机系统可以具有例如包括可操作地耦合到存储器并被配置为管理存储器的存储器管理单元(MMU)的中央处理单元(CPU)。 存储器管理单元(MMU)可以管理存储器,使得存储器存储布置在多个存储器页面中的数据。 公开了一种用于提供用于存储布置在多个存储器页内的数据的存储器的访问安全性的方法。