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11. 发明授权

US07487505B2 Multithreaded microprocessor with register allocation based on number of active threads 有权
标题翻译：基于活动线程数的多线程微处理器，具有寄存器分配
公开(公告)号：US07487505B2
公开(公告)日：2009-02-03
申请号：US10212945
申请日：2002-08-05
申请人： Mark B. Rosenbluth , Gilbert Wolrich , Debra Bernstein
发明人： Mark B. Rosenbluth , Gilbert Wolrich , Debra Bernstein
IPC分类号： G06F9/46 , G06F15/00 , G06F15/76 , G06F7/38 , G06F9/00 , G06F9/44 , G06F12/00 , G06F12/02
CPC分类号： G06F9/3885 , G06F9/30098 , G06F9/30123 , G06F9/3851
摘要： A mechanism in a multithreaded processor to allocate resources based on configuration information indicating how many threads are in use.
摘要翻译：多线程处理器中基于配置信息分配资源的机制，该配置信息指示正在使用多少线程。

12. 发明授权

US08380923B2 Queue arrays in network devices 有权
公开(公告)号：US08380923B2
公开(公告)日：2013-02-19
申请号：US12941802
申请日：2010-11-08
申请人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein
发明人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein
IPC分类号： G06F13/00 , G06F12/08 , G06F3/00 , H04L12/28
CPC分类号： G06F12/0875 , H04L49/90 , H04L49/901
摘要： A queue descriptor including a head pointer pointing to the first element in a queue and a tail pointer pointing to the last element in the queue is stored in memory. In response to a command to perform an enqueue or dequeue operation with respect to the queue, fetching from the memory to a cache only one of either the head pointer or tail pointer and returning to the memory from the cache portions of the queue descriptor modified by the operation.

13. 发明授权

US07895239B2 Queue arrays in network devices 有权
标题翻译：网络设备中的队列数组
公开(公告)号：US07895239B2
公开(公告)日：2011-02-22
申请号：US10039289
申请日：2002-01-04
申请人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein
发明人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein
IPC分类号： G06F17/30 , G06F3/00 , G06F13/36 , H04L12/28
CPC分类号： G06F12/0875 , H04L49/90 , H04L49/901
摘要： A queue descriptor including a head pointer pointing to the first element in a queue and a tail pointer pointing to the last element in the queue is stored in memory. In response to a command to perform an enqueue or dequeue operation with respect to the queue, fetching from the memory to a cache only one of either the head pointer or tail pointer and returning to the memory from the cache portions of the queue descriptor modified by the operation.
摘要翻译：包括指向队列中的第一个元素的头指针和指向队列中最后一个元素的尾指针的队列描述符存储在内存中。响应于执行相对于队列的入队或出队操作的命令，从存储器获取仅缓存头指针或尾指针中的一个，并从由队列描述符修改的队列描述符的高速缓存部分返回到存储器的操作。

14. 发明授权

US07313140B2 Method and apparatus to assemble data segments into full packets for efficient packet-based classification 有权
标题翻译：将数据段组合成完整分组的方法和装置，用于有效的基于分组的分类
公开(公告)号：US07313140B2
公开(公告)日：2007-12-25
申请号：US10188087
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Raymond Ng , Debra Bernstein , Mark B. Rosenbluth
发明人： Sridhar Lakshmanamurthy , Charles E. Narad , Lawrence B. Huston , Yim Pun , Raymond Ng , Debra Bernstein , Mark B. Rosenbluth
IPC分类号： H04L12/28
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9047
摘要： A method may be used for assembling received data segments into full packets in an initial processing stage in a processor. The method may include receiving a plurality of data segments from a packet and determining a first storage location for each of the plurality of data segments. The method may further include storing each of the plurality of data segments in its determined first storage location and determining a second storage location for each of the plurality of data segments, the second storage locations being logically ordered to represent the order the data segments originally occurred in the packet. The method may also include storing each of the plurality of data segments in its determined second storage location to re-assemble the packet and releasing the first storage location associated with each data segment after storing the data segment in its determined second storage location. The method may additionally include, upon the storing of an end of packet data segment from the packet in its determined second storage location, passing control of the plurality of related data segments to a next processing stage in the processor.
摘要翻译：可以在处理器的初始处理阶段中使用一种方法将接收的数据段组装成全分组。该方法可以包括从分组接收多个数据段并且确定多个数据段中的每一个的第一存储位置。该方法还可以包括将多个数据段中的每一个存储在其确定的第一存储位置中，并且为多个数据段中的每一个确定第二存储位置，第二存储位置被逻辑地排序以表示数据段最初发生的顺序在包中。该方法还可以包括将多个数据段中的每一个存储在其确定的第二存储位置中以在将数据段存储在其确定的第二存储位置之后重新组合分组并释放与每个数据段相关联的第一存储位置。该方法可以另外包括在从分组在其确定的第二存储位置中存储分组数据段的结束时，将多个相关数据段的控制传递到处理器中的下一个处理阶段。

15. 发明授权

US07437724B2 Registers for data transfers 有权
标题翻译：注册数据传输
公开(公告)号：US07437724B2
公开(公告)日：2008-10-14
申请号：US10116670
申请日：2002-04-03
申请人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Matthew J. Adiletta , Hugh M. Wilkinson, III
发明人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Matthew J. Adiletta , Hugh M. Wilkinson, III
IPC分类号： G06F9/46 , G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/4843 , G06F9/30101 , G06F9/3012 , G06F9/30123 , G06F9/3851
摘要： A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.
摘要翻译：一种用于在多个硬件上下文和编程引擎中采用用于数据传输的寄存器以便于高性能数据处理的系统和方法。该系统和方法包括处理器，其包括具有寄存器的编程引擎，用于将驻留在执行编程引擎中的寄存器中的一个寄存器中的数据传送到驻留在相邻编程引擎中的后续寄存器中的寄存器。

16. 发明授权

US07324520B2 Method and apparatus to process switch traffic 有权
标题翻译：处理交换机流量的方法和装置
公开(公告)号：US07324520B2
公开(公告)日：2008-01-29
申请号：US10188419
申请日：2002-07-03
申请人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Debra Bernstein , Hugh M. Wilkinson, III , Mark B. Rosenbluth
发明人： Sridhar Lakshmanamurthy , Lawrence B. Huston , Debra Bernstein , Hugh M. Wilkinson, III , Mark B. Rosenbluth
IPC分类号： H04L12/28
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9047 , H04L49/9073
摘要： A system and method for reassembling c-frames into coherent packets are disclosed. C-frames contain segments of a data set. A micro-engine operating multiple threads copies the data set segments into assigned queues, following a thread hierarchy to keep the segments in order. The queues are stored in SRAM. The micro-engine maintains a subset of the total number of queues in local memory. If a segment belongs to a queue not in local memory, the least recently used queue is copied to SRAM, the required queue is read from SRAM, and the queue is updated with the data set segment.
摘要翻译：公开了一种用于将c帧重新组合成相干分组的系统和方法。 C帧包含数据集的段。运行多个线程的微引擎将数据集段复制到分配的队列中，遵循线程层次结构以保持段的顺序。队列存储在SRAM中。微引擎维护本地内存中队列总数的一个子集。如果段属于不在本地存储器中的队列，则将最近最少使用的队列复制到SRAM，从SRAM读取所需的队列，并且使用数据集段更新队列。

17. 发明授权

US07302549B2 Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access 有权
标题翻译：处理使用相同功能的数据包序列设置流水线多个线程跨越多个处理引擎并具有独占数据访问
公开(公告)号：US07302549B2
公开(公告)日：2007-11-27
申请号：US11092366
申请日：2005-03-29
申请人： Hugh M. Wilkinson, III , Matthew J. Adiletta , Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Myles J. Wilde
发明人： Hugh M. Wilkinson, III , Matthew J. Adiletta , Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein , Myles J. Wilde
IPC分类号： G06F9/46
CPC分类号： G06F15/8053
摘要： A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes processing a sequence of packets with a sequence of threads, with the sequence of threads spanning multiple programmable processing elements integrated within a processor, and with the programmable processing elements providing multiple threads of execution such that each of the threads acquires exclusive modification access to data shared.
摘要翻译：一种用于在功能管线中采用多个硬件上下文和编程引擎的系统和方法，该功能管线被划分以便于高性能数据处理。该系统和方法包括用线程序列处理一系列分组，其中线程序列跨越集成在处理器内的多个可编程处理元件，并且可编程处理元件提供多个执行线程，使得每个线程获得排他性修改访问数据共享。

18. 发明授权

US07225281B2 Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms 有权
标题翻译：多处理器基础设施，通过单独的数据总线，控制总线和支持机制的多个实例提供灵活的带宽分配
公开(公告)号：US07225281B2
公开(公告)日：2007-05-29
申请号：US10212944
申请日：2002-08-05
申请人： Mark B. Rosenbluth , Gilbert Wolrich , Debra Bernstein , Myles J. Wilde , Matthew J. Adiletta
发明人： Mark B. Rosenbluth , Gilbert Wolrich , Debra Bernstein , Myles J. Wilde , Matthew J. Adiletta
IPC分类号： G06F13/00
CPC分类号： G06F13/364 , G06F13/4004
摘要： A bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses. Commands are generated by bus masters and are interpreted by bus targets on a per-target basis. Each bus target controls the servicing of a command intended for such target by controlling the transfer of push data over the push bus to a bus master specified in the command as a destination, for a push operation type, and by controlling the transfer of pull data over the pull bus to the target from a bus master specified in the command as a destination, for a pull operation type. Arbitration logic associated with each bus is used to control the flow of the information exchanges on that bus.
摘要翻译：一种总线机制，用于通过总线结构控制总线主机和总线目标之间的信息交换，该总线结构包括单独的命令，推拉数据总线。命令由公交车主人生成，并由每个目标的公交车目标解释。每个总线目标通过控制通过推送总线将推送数据传送到作为目的地的命令中指定的总线主机，用于推送操作类型，并通过控制拉动数据的传送来控制对该目标的命令的服务通过从作为目的地的命令中指定的总线主机到目的地的拉取总线，用于拉动操作类型。与每个总线相关联的仲裁逻辑用于控制该总线上的信息交换流。

19. 发明授权

US07181594B2 Context pipelines 有权
标题翻译：上下文管道
公开(公告)号：US07181594B2
公开(公告)日：2007-02-20
申请号：US10057723
申请日：2002-01-25
申请人： Hugh M. Wilkinson, III , Mark B. Rosenbluth , Matthew J. Adiletta , Debra Bernstein , Gilbert Wolrich
发明人： Hugh M. Wilkinson, III , Mark B. Rosenbluth , Matthew J. Adiletta , Debra Bernstein , Gilbert Wolrich
IPC分类号： G06F9/312
CPC分类号： G06F9/462 , G06F9/30123
摘要： A method of parallel hardware-based multithreaded processing is described. The method includes assigning tasks for packet processing to programming engines and establishing pipelines between programming stages, which correspond to the programming engines. The method also includes establishing contexts for the assigned tasks on the programming engines and using a software controlled cache such as a CAM to transfer data between next neighbor registers residing in the programming engines.
摘要翻译：描述了一种基于并行硬件的多线程处理方法。该方法包括将分组处理的任务分配给编程引擎，并在与编程引擎相对应的编程阶段之间建立管线。该方法还包括为编程引擎上分配的任务建立上下文，并使用诸如CAM的软件控制的高速缓存来在驻留在编程引擎中的下一个相邻寄存器之间传送数据。

20. 发明授权

US07181573B2 Queue array caching in network devices 失效
标题翻译：网络设备中的队列阵列缓存
公开(公告)号：US07181573B2
公开(公告)日：2007-02-20
申请号：US10041678
申请日：2002-01-07
申请人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein
发明人： Gilbert Wolrich , Mark B. Rosenbluth , Debra Bernstein
IPC分类号： G06F12/00
CPC分类号： H04L49/9047 , G06F12/0875 , H04L45/7453 , H04L49/90 , H04L49/901 , H04L49/9021
摘要： In response to receiving a request to perform an enqueue or dequeue operation a corresponding queue descriptor specifying the structure of the queue is referenced to execute the operation. The queue descriptor is stored in a processor's memory controller logic.
摘要翻译：响应于接收到执行入队或出队操作的请求，引用指定队列结构的对应队列描述符来执行该操作。队列描述符存储在处理器的存储器控制器逻辑中。

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