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11. 发明授权

US06138223A Absolute address history table index generation for predicting instruction and operand cache accesses 失效
标题翻译：用于预测指令和操作数缓存访问的绝对地址历史表索引生成
公开(公告)号：US06138223A
公开(公告)日：2000-10-24
申请号：US70361
申请日：1998-04-30
申请人： Mark Anthony Check , John Stephen Liptay
发明人： Mark Anthony Check , John Stephen Liptay
IPC分类号： G06F9/32 , G06F9/38 , G06F12/10
CPC分类号： G06F9/3806 , G06F12/0888 , G06F12/1054 , G06F9/322 , G06F9/3826 , G06F9/3832
摘要： A computer processor that uses an AAHT to provide a guess at the real (absolute) address bits used to access the cache and directories that is more accurate in a high-frequency design which prevents any sort of full or large partial adds of ranges of base, index, or displacement has two index values generated and two AAHT arrays, one each for instruction and operand logical requests. It handles cases in which the data is not directly from the GPR array. For designs that aim at improving performance data for some operations that update GPR's may be used for address generation prior to the execution and write to the GPR array, these include data bypass for Load Address (LA) and Load (L). The system handles instruction fetches, relative branches, other special instruction address instruction fetch requests, and those started as a result of a branch history table (BHT) predicted instruction fetch. A method for AAHT synonym resolution improves the accuracy of the index value for an Absolute Address History Table buffer.
摘要翻译：使用AAHT的计算机处理器提供用于访问高速缓存的实际（绝对）地址位和在高频设计中更精确的目录的猜测，其防止基本范围的任何类型的全部或大部分添加，索引或位移具有两个生成的索引值和两个AAHT数组，一个用于指令和操作数逻辑请求。它处理数据不直接来自GPR数组的情况。对于旨在改进性能数据的设计，更新GPR可能会在执行和写入GPR阵列之前产生地址，这些操作包括负载地址（LA）和负载（L）的数据旁路。系统处理指令提取，相对分支，其他特殊指令地址指令取出请求以及作为分支历史表（BHT）预测指令获取结果启动的指令。 AAHT同义词分辨率的方法提高了绝对地址历史记录表缓冲区的索引值的准确性。

12. 发明授权

US5713035A Linking program access register number with millicode operand access 失效
标题翻译：将程序访问寄存器编号与millicode操作数访问连接
公开(公告)号：US5713035A
公开(公告)日：1998-01-27
申请号：US414164
申请日：1995-03-31
申请人： Mark Steven Farrell , Barry Watson Krumm , John Stephen Liptay , Charles Franklin Webb , Steven QiHong Ying
发明人： Mark Steven Farrell , Barry Watson Krumm , John Stephen Liptay , Charles Franklin Webb , Steven QiHong Ying
IPC分类号： G06F9/318 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3017 , G06F9/3836 , G06F9/384 , G06F9/3863
摘要： In a milli-mode processor, bits (0-6) of an access list entry token (ALET) in the program access register must be zeros in order for access register translation to be successful. When the ALET is being copied from a program access register to a millicode access register, bits 0-3 of ALET, written into the millicode access register, are set to the access register number of the program access register from which the data is being read. This establishes the affinity between the program access register number and any logical fetches which might be attempted by millicode.
摘要翻译：在毫模式处理器中，程序访问寄存器中访问列表条目标记（ALET）的位（0-6）必须为零，以使访问寄存器转换成功。当将ALET从程序访问寄存器复制到一个毫代数据访问寄存器时，写入该程序存取寄存器的ALET位0-3被设置为读取数据的程序访问寄存器的访问寄存器号。这建立了程序访问寄存器编号与可能由millicode尝试的任何逻辑提取之间的亲和度。

13. 发明授权

US5649155A Cache memory accessed by continuation requests 失效
标题翻译：缓存由连续请求访问
公开(公告)号：US5649155A
公开(公告)日：1997-07-15
申请号：US414176
申请日：1995-03-31
申请人： Barry Watson Krumm , Steven Tyler Comfort , Jin Ji , John Stephen Liptay , Charles Franklin Webb , David Man Chow Wong , Steven QiHong Ying
发明人： Barry Watson Krumm , Steven Tyler Comfort , Jin Ji , John Stephen Liptay , Charles Franklin Webb , David Man Chow Wong , Steven QiHong Ying
IPC分类号： G06F9/34 , G06F9/38 , G06F12/08 , G06F12/10 , G06F12/04
CPC分类号： G06F9/3812 , G06F12/0815 , G06F12/0851 , G06F12/0882 , G06F9/34 , G06F9/383 , G06F12/1054
摘要： In a cache memory system, continuation registers are provided to abbreviated address data identifying the line position in the cache memory from which data is fetched. When data is fetched from a line in said cache memory, the bin number and line position identification of the line in the cache memory are saved in a continuation register. Then, subsequently, when data is fetched from the same line, it is fetched by a continuation request wherein the data saved in the continuation register is used to access the cache memory. The continuation registers provide the abbreviated address data for comparison in both PSC (program store compare) and OSC (operand store compare).
摘要翻译：在高速缓冲存储器系统中，连续寄存器被提供给缩写地址数据，以标识从其获取数据的高速缓冲存储器中的行位置。当从所述高速缓冲存储器中的行中取出数据时，高速缓冲存储器中的行的仓号和行位置标识被保存在连续寄存器中。然后，随后，当从相同的行取出数据时，它被继续请求取出，其中保存在连续寄存器中的数据用于访问高速缓冲存储器。继续寄存器提供用于在PSC（程序存储比较）和OSC（操作数存储比较）中进行比较的缩写地址数据。

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