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11. 发明授权

US06617069B1 Battery over-discharge protection 有权
标题翻译：电池过放电保护
公开(公告)号：US06617069B1
公开(公告)日：2003-09-09
申请号：US09787346
申请日：2001-03-16
申请人： George Frederick Hopper , Richard Penneck , Masanori Furuta , Takashi Sato , Shigefumi Torii
发明人： George Frederick Hopper , Richard Penneck , Masanori Furuta , Takashi Sato , Shigefumi Torii
IPC分类号： H01M1048
CPC分类号： H01M2/348 , H01M2/1241 , H01M2/34 , H01M6/10 , H01M10/4257 , H01M10/48 , H01M2200/00 , H02H7/18 , H02H9/026 , H02J7/0031
摘要： The present invention relates to an over-discharge preventing circuit, especially an over-discharge over-current preventing circuit, and more specifically relates to an over-discharge over-current preventing circuit comprising an over-discharge preventing circuit having a FET and an over-current preventing circuit for protecting the FET. The invention includes a primary or secondary battery containing such a circuit, and a battery pack containing such a circuit. The batteries comprising an over-discharge over-current preventing circuit according to the present invention have (1) an electrolyte, (2) a pair of electrode members forming a negative electrode member and a positive electrode member which electrically contact the electrolyte, (3) a pair of external connection terminals respectively electrically connected to corresponding electrode members and (4) a PTC element and FET with a source terminal and drain terminal serially connected between one of the electrode members and the corresponding external connection terminal, the gate terminal being connected to the other electrode member. The FET prevents over-discharge by stopping the supply of current to the external connection terminal when the voltage between the electrode members becomes lower than a predetermined value. The PTC element prevents over-current by stopping the supply of current to the external terminal when the current between the electrode members exceeds a predetermined value, thereby also protecting the FET from being destroyed by such an over-current.
摘要翻译：过放电防止电路技术领域本发明涉及过放电防止电路，特别是过放电过电流防止电路，更具体地涉及一种过放电过电流防止电路，其包括具有FET和过放电防止电路的过放电防止电路用于保护FET的电流防护电路。本发明包括含有这种电路的主电池或二次电池，以及包含这种电路的电池组。包括根据本发明的过放电过电流防止电路的电池具有（1）电解质，（2）形成负极部件的一对电极部件和与电解质电接触的正极部件（3））一对外部连接端子，分别与相应的电极部件电连接，以及（4）PTC元件和FET，其源极端子和漏极端子串联连接在一个电极部件和对应的外部连接端子之间，栅极端子被连接到另一个电极部件。当电极构件之间的电压变得低于预定值时，FET通过停止向外部连接端子的电流供应来防止过度放电。当元件之间的电流超过预定值时，PTC元件通过停止向外部端子的电流供应来防止过电流，从而也可以防止FET被这种过电流破坏。

12. 发明授权

US08730083B2 Analog-digital converter with calibration and receiver including the converter 有权
标题翻译：具有校准和接收器的模数转换器包括转换器
公开(公告)号：US08730083B2
公开(公告)日：2014-05-20
申请号：US13610499
申请日：2012-09-11
申请人： Hirotomo Ishii , Tomohiko Sugimoto , Masanori Furuta
发明人： Hirotomo Ishii , Tomohiko Sugimoto , Masanori Furuta
IPC分类号： H03M1/12
CPC分类号： H03M1/687 , H03M1/468 , H03M1/765 , H03M1/804
摘要： According to an embodiment, there are provided a capacitor DAC for generating an output signal in accordance with a connection state of a capacitor element, a reference voltage generation circuit for supplying a reference voltage to the capacitor DAC, a comparator for outputting a comparison result in accordance with the output signal, a successive approximation register for outputting a digital signal in accordance with the comparison result, and a control circuit for controlling a connection state of the capacitor element in accordance with the comparison result and comparing an ideal code with a digital signal obtained by sampling a predetermined voltage, thereby correcting an error of the digital signal.
摘要翻译：根据实施例，提供了一种用于根据电容器元件的连接状态产生输出信号的电容器DAC，用于向电容器DAC提供参考电压的参考电压产生电路，用于输出比较结果的比较器根据输出信号，根据比较结果输出数字信号的逐次逼近寄存器和用于根据比较结果控制电容器元件的连接状态并将理想代码与数字信号进行比较的控制电路通过对预定电压进行采样获得，从而校正数字信号的误差。

13. 发明授权

US08619925B2 Automatic gain control circuit and receiver circuit 失效
标题翻译：自动增益控制电路和接收电路
公开(公告)号：US08619925B2
公开(公告)日：2013-12-31
申请号：US12719327
申请日：2010-03-08
申请人： Takayuki Takida , Masanori Furuta
发明人： Takayuki Takida , Masanori Furuta
IPC分类号： H04L27/08
CPC分类号： H03F3/189 , H03F2200/294 , H03F2200/451 , H03F2200/78 , H03G3/3052 , H03G3/3089
摘要： An automatic gain control circuit configured so that a response time is reduced until a gain converges is disclosed. A variable gain amplifier is configured so that a gain is varied by a first control signal. A detector circuit detects an intensity of an output signal of the variable gain amplifier. A comparator compares an output signal of the detector circuit with a reference signal. An integrator integrates a signal corresponding to an output signal of the comparator, and outputs an integration result to the variable gain amplifier as the first control signal. A loop gain control unit, connected between the comparator and the integrator, is configured so that a loop gain is varied by a second control signal. A level detection unit detects an intensity of an output signal of the integrator and outputs a detection result to the loop gain control unit as the second control signal.
摘要翻译：公开了一种自动增益控制电路，其被配置为使得响应时间缩短直到增益收敛。可变增益放大器被配置为使得增益被第一控制信号改变。检测器电路检测可变增益放大器的输出信号的强度。比较器将检测器电路的输出信号与参考信号进行比较。积分器对与比较器的输出信号相对应的信号进行积分，并将积分结果输出到可变增益放大器作为第一控制信号。连接在比较器和积分器之间的环路增益控制单元被配置为使得环路增益被第二控制信号改变。电平检测单元检测积分器的输出信号的强度，并将检测结果输出到环路增益控制单元作为第二控制信号。

14. 发明授权

US08462038B2 A/D converter and radio receiver 失效
标题翻译： A / D转换器和无线电接收器
公开(公告)号：US08462038B2
公开(公告)日：2013-06-11
申请号：US13409841
申请日：2012-03-01
申请人： Masanori Furuta
发明人： Masanori Furuta
IPC分类号： H03M1/34
CPC分类号： H03M1/0697 , H03M1/468
摘要： There is provided a successive-approximation A/D converter in which the binary weighted capacitive D/A converter generates a residual signal for each of cycles assigned to each bit of N bits on the basis of an analog input signal and a reference voltage, the first comparator compares a residual signal at a first time point within a cycle with a predetermined voltage to acquire a first comparison result, the register stores the first comparison result therein, the second comparator compares a residual signal at a second time point later than the first time point within the cycle with the predetermined voltage to acquire a second comparison result, the error determining circuit generates an error detection signal when they differ from each other, and the error-correcting circuit inverts and outputs the first comparison result from the register in a case that the error detection signal has been generated.
摘要翻译：提供了逐次逼近A / D转换器，其中二进制加权电容性D / A转换器基于模拟输入信号和参考电压为分配给N位的每个位的每个周期产生残留信号，第一比较器将周期内的第一时间点的残留信号与预定电压进行比较，以获得第一比较结果，寄存器存储第一比较结果，第二比较器比第一比较结果比第一比较结果在所述周期内具有预定电压的时间点以获取第二比较结果，所述误差确定电路当它们彼此不同时产生误差检测信号，并且所述误差校正电路将所述寄存器中的第一比较结果反转并输出已经生成了错误检测信号的情况。

15. 发明申请

US20130076545A1 TIME ERROR ESTIMATING DEVICE, ERROR CORRECTION DEVICE AND A/D CONVERTER 失效
标题翻译：时间错误估计装置，错误校正装置和A / D转换器
公开(公告)号：US20130076545A1
公开(公告)日：2013-03-28
申请号：US13425332
申请日：2012-03-20
申请人： Tomohiko Sugimoto , Takafumi Yamaji , Junya Matsuno , Masanori Furuta
发明人： Tomohiko Sugimoto , Takafumi Yamaji , Junya Matsuno , Masanori Furuta
IPC分类号： G06F11/00 , G06F11/07 , H03M1/06
CPC分类号： H03M1/0836 , H03M1/1215
摘要： A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value.
摘要翻译：一种时间误差估计装置，用于当采样电路通过在彼此偏移的定时进行采样产生多个采样输出信号时，估计多个采样电路中的每一个的采样时间误差，具有各自被配置为获得表示基于通过调整相关值的权重而获得的结果，采样输出信号之间的相似度和配置为估计采样电路的采样时间误差的加权加法器。

16. 发明申请

US20120056770A1 SUCCESSIVE APPROXIMATION REGISTER-ANALOG DIGITAL CONVERTER AND RECEIVER 失效
标题翻译：成功的近似寄存器模拟数字转换器和接收器
公开(公告)号：US20120056770A1
公开(公告)日：2012-03-08
申请号：US13035202
申请日：2011-02-25
申请人： Mai ARAKI , Masanori Furuta
发明人： Mai ARAKI , Masanori Furuta
IPC分类号： H03M1/12 , H03L7/06
CPC分类号： H03M1/466 , H03M1/78
摘要： An SAR-ADC includes input and reference terminals, first and second capacitor sets, a dummy capacitor, a comparator, a switch, and a logic. The first and second capacitor sets include first and second capacitors, respectively. The first capacitor has a first capacitance. The second capacitor has a second capacitance. The dummy capacitor has a third capacitance. The comparator compares an output voltage with a ground voltage and outputs a digital output code in accordance with a difference between the output and ground voltages. The switch is connected among the first capacitors of the first and second capacitor sets, and the reference terminal. The logic turns the switch based on the digital output code. The input terminal is located between the first and second capacitors of the first capacitor set. The second capacitor of the first capacitor set is located between the first and second capacitors of the second capacitor set.
摘要翻译： SAR-ADC包括输入和参考端子，第一和第二电容器组，虚拟电容器，比较器，开关和逻辑。第一和第二电容器组分别包括第一和第二电容器。第一电容器具有第一电容。第二电容器具有第二电容。虚拟电容器具有第三电容。比较器将输出电压与接地电压进行比较，并根据输出和接地电压之间的差输出数字输出代码。开关连接在第一和第二电容器组的第一电容器和参考端子之间。逻辑根据数字输出代码开关。输入端子位于第一电容器组的第一和第二电容器之间。第一电容器组的第二电容器位于第二电容器组的第一和第二电容器之间。

17. 发明申请

US20100150270A1 SIGNAL PROCESSING CIRCUIT AND RECEIVER USING THE SAME 审中-公开
标题翻译：使用信号处理电路和接收器
公开(公告)号：US20100150270A1
公开(公告)日：2010-06-17
申请号：US12558765
申请日：2009-09-14
申请人： Masanori Furuta , Takafumi Yamaji
发明人： Masanori Furuta , Takafumi Yamaji
IPC分类号： H04L27/22
CPC分类号： H04L27/22 , H04L27/38
摘要： A signal processing circuit includes a decimation filter which down-samples over-sampled first three-phase digital signals to obtain second three-phase digital signals, and a converter which subjects the second three-phase digital signals to a three-phase to IQ conversion, and obtains orthogonal digital signals.
摘要翻译：信号处理电路包括抽样滤波器，对抽样的过采样的第一三相数字信号进行下采样以获得第二三相数字信号;以及转换器，其使第二三相数字信号进行三相到IQ转换并获得正交数字信号。

18. 发明授权

US08154917B2 Magnetic storage device 失效
标题翻译：磁存储装置
公开(公告)号：US08154917B2
公开(公告)日：2012-04-10
申请号：US13039633
申请日：2011-03-03
申请人： Masanori Furuta , Daisuke Kurose , Tsutomu Sugawara
发明人： Masanori Furuta , Daisuke Kurose , Tsutomu Sugawara
IPC分类号： G11C11/14
CPC分类号： G11C7/14 , G11C7/02 , G11C7/067 , G11C11/1659 , G11C11/1673
摘要： A magnetic storage device includes a plurality of MRAM memory cells connected to a data transfer line, a clamp transistor connected between the data transfer line and a reading signal line and configured to fixedly hold the potential of the data transfer line, and a reading circuit which is connected to the reading signal line and which reads the storage information of the memory cell. The reading circuit includes a hold switch connected between the reading signal line and a reading node N and configured to hold the potential of the node N, a capacitor connected between the node N and a ground end, a precharging switch connected between the node N and a power source and configured to charge the capacitor, and an inverter to which the potential of the node N is input to generate a digital signal.
摘要翻译：磁存储装置包括连接到数据传输线的多个MRAM存储单元，连接在数据传送线和读取信号线之间并被配置为固定地保持数据传输线的电位的钳位晶体管，以及读取电路，连接到读取信号线并读出存储单元的存储信息。读取电路包括连接在读取信号线和读取节点N之间并被配置为保持节点N的电位的保持开关，连接在节点N和接地端之间的电容器，连接在节点N和节点N之间的预充电开关电源，并且被配置为对电容器充电;以及逆变器，输入节点N的电位以产生数字信号。

19. 发明授权

US08040271B2 A/D conversion apparatus, A/D conversion method, and communication apparatus 有权
标题翻译： A / D转换装置，A / D转换方法和通信装置
公开(公告)号：US08040271B2
公开(公告)日：2011-10-18
申请号：US12553315
申请日：2009-09-03
申请人： Masanori Furuta , Tomohiko Ito , Tetsuro Itakura
发明人： Masanori Furuta , Tomohiko Ito , Tetsuro Itakura
IPC分类号： H03M1/38
CPC分类号： H04L27/06 , H03M1/0682 , H03M1/468 , H03M1/804
摘要： An A/D conversion apparatus includes: a first and a second D/A converter to sample an analog signal and successively compare the analog signal and a reference signal to generate a first and a second comparison signal respectively; a first comparator to compare the first comparison signal generated by the first D/A converter with a benchmark signal; a second comparator to compare the second comparison signal generated by the second D/A converter with the benchmark signal; and a converter to convert the analog signal to a digital signal according to results of the comparisons by the first and second comparators.
摘要翻译： A / D转换装置包括：第一和第二D / A转换器，对模拟信号进行采样，并连续地比较模拟信号和参考信号，分别产生第一和第二比较信号; 第一比较器，用于将由第一D / A转换器产生的第一比较信号与基准信号进行比较; 第二比较器，用于将由第二D / A转换器产生的第二比较信号与基准信号进行比较; 以及根据第一和第二比较器的比较结果将模拟信号转换为数字信号的转换器。

20. 发明授权

US08009484B2 Read circuit and read method 有权
标题翻译：读电路和读方法
公开(公告)号：US08009484B2
公开(公告)日：2011-08-30
申请号：US12547945
申请日：2009-08-26
申请人： Masanori Furuta , Daisuke Kurose , Tsutomu Sugawara
发明人： Masanori Furuta , Daisuke Kurose , Tsutomu Sugawara
IPC分类号： G11C7/10 , G11C11/00
CPC分类号： G11C29/12 , G11C11/1673 , G11C13/004 , G11C27/024 , G11C29/1201 , G11C29/50 , G11C2013/0057
摘要： In a read circuit, a write circuit writes a data to be stored and/or a test data to the memory cell. A control circuit controls the write circuit to write the test data to the memory cell in a first phase, and to write the test data which is same as the first phase to the memory cell in a second phase. An integrator integrates voltages at one terminal of the memory cell during the first phase to obtain a first integrated voltage, and integrates voltages at one terminal of the memory cell during the second phase to obtain a second integrated voltage. A buffer stores the first integrated voltage. A comparator compares the first integrated voltage from the buffer with the second integrated voltage from the integrator to obtain the data.
摘要翻译：在读取电路中，写入电路将要存储的数据和/或测试数据写入存储单元。控制电路控制写入电路，以第一阶段将测试数据写入存储单元，并将与第一阶段相同的测试数据写入第二阶段的存储单元。积分器在第一阶段中将存储单元的一个端子处的电压进行积分，以获得第一积分电压，并且在第二阶段期间对存储单元的一个端子处的电压进行积分，以获得第二积分电压。缓冲器存储第一集成电压。比较器比较来自缓冲器的第一集成电压和来自积分器的第二集成电压以获得数据。

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