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11. 发明申请

WO2010030799A1 STACKED DEVICE IDENTIFICATION ASSIGNMENT 审中-公开
标题翻译：堆叠设备标识分配
公开(公告)号：WO2010030799A1
公开(公告)日：2010-03-18
申请号：PCT/US2009/056538
申请日：2009-09-10
申请人： MICRON TECHNOLOGY, INC. , KEETH, Brent
发明人： KEETH, Brent
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： G11C5/02 , G11C5/06 , G11C7/10 , G11C7/20 , G11C2207/2227 , H01L23/12 , H01L23/48 , H01L2224/05001 , H01L2224/05009 , H01L2224/0557 , H01L2224/05571 , H01L2224/16145 , H01L2924/00014 , H01L2224/05599 , H01L2224/05099
摘要： Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die.
摘要翻译：一些实施例包括具有布置在堆叠中的骰子的装置和方法。骰子至少包括第一管芯和第二管芯，以及连接到管芯的连接。连接可以被配置为在将第一标识分配给第一管芯期间将控制信息传送到第一管芯，并且在将第二标识分配给第二管芯期间将控制信息从第一管芯传送到第二管芯。

12. 发明申请

WO2006118788A2 SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE 审中-公开
标题翻译：基于命令信号和操作状态解码命令的系统和方法
公开(公告)号：WO2006118788A2
公开(公告)日：2006-11-09
申请号：PCT/US2006/014650
申请日：2006-04-17
申请人： MICRON TECHNOLOGY, INC. , JANZEN, Jeffrey, W. , KEETH, Brent , WRIGHT, Jeffrey, P. , CULLUM, James, S.
发明人： JANZEN, Jeffrey, W. , KEETH, Brent , WRIGHT, Jeffrey, P. , CULLUM, James, S.
IPC分类号： G06F13/00
CPC分类号： G11C11/4096 , G11C7/1072 , G11C11/40611 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
摘要翻译：一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产生内部控制信号，以根据命令信号和操作状态进行操作。命令信号的相同组合可以根据操作状态请求不同的命令。当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令州。

13. 发明申请

WO2004084225A1 METHOD AND APPARATUS FOR ESTABLISHING AND MAINTAINING DESIRED READ LATENCY IN HIGH-SPEED DRAM 审中-公开
标题翻译：用于建立和维护高速DRAM中所需读取延迟的方法和装置
公开(公告)号：WO2004084225A1
公开(公告)日：2004-09-30
申请号：PCT/US2004/007980
申请日：2004-03-16
申请人： MICRON TECHNOLOGY, INC.
发明人： JOHNSON, Brian , KEETH, Brent , LIN, Feng
IPC分类号： G11C7/10
CPC分类号： G11C7/222 , G11C7/1072 , G11C11/4076
摘要： A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve and specified read latency. A rester signal is generated at DRAM initialization and starts an first counter, which counts external clock cycles, and is also passed through the slave delay line of the delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.
摘要翻译：一种用于管理从外部时钟信号导出的内部时钟信号的可变定时的方法和装置，以便补偿相对于数据流的读取时钟反馈定时的量的不确定性和变化，以实现和指定的读延迟。在DRAM初始化时产生恢复信号，并启动计数外部时钟周期的第一计数器，并且还通过延迟锁定循环的从延迟线来启动第二个计数器。一旦启动，计数器连续运行，计数值的差值代表作为外部时钟信号的内部延迟。内部读延迟值用于抵消DRAM电路的内部读延迟。一旦非偏移计数器等效于偏移计数器，读取数据将放置在具有指定读延迟并与外部读时钟同步的输出线上。

14. 发明申请

WO2002099661A3 METHOD AND APPARATUS FOR DETERMINING ACTUAL WRITE LATENCY AND ACCURATELY ALIGNING THE START OF DATA CAPTURE WITH THE ARRIVAL OF DATA AT A MEMORY DEVICE 审中-公开
公开(公告)号：WO2002099661A3
公开(公告)日：2002-12-12
申请号：PCT/US2002/017849
申请日：2002-06-06
申请人： MICRON TECHNOLOGY, INC.
发明人： JOHNSON, Brian , KEETH, Brent , MANNING, Troy, A.
IPC分类号： G11C7/10
摘要： A method and apparatus for accurately determining the actual arrival of data at a memory device relative to the write clock to accurately align the start of data capture and the arrival of the data at the memory device is disclosed. The actual time of arrival of data at the inputs to a memory device is determined by sending back-to-back write commands along with the predetermined data pattern to the memory device. The data pattern is stored in a register and any difference between the predicted arrival time of the data and the actual arrival time of the data is determined by logic circuitry. Any determined difference can then be compensated for by delaying the start of the capture of the data at the memory device, thereby accurately aligning the start of the data capture and the arrival of the data at the memory device.

15. 发明申请

WO1997008700A1 REDUCED AREA SENSE AMPLIFIER ISOLATION LAYOUT IN A DYNAMIC RAM ARCHITECTURE 审中-公开
标题翻译：动态RAM架构中的降低区域感测放大器隔离布局
公开(公告)号：WO1997008700A1
公开(公告)日：1997-03-06
申请号：PCT/US1996013657
申请日：1996-08-23
申请人： MICRON TECHNOLOGY, INC.
发明人： MICRON TECHNOLOGY, INC. , KEETH, Brent
IPC分类号： G11C07/00
CPC分类号： G11C7/18 , G11C7/065 , G11C11/4091
摘要： A memory device has an array of memory cells which are positioned in a first block and a second block. The memory cells are arranged in rows and columns. A plurality of bit lines is coupled to the memory cells and a plurality of word lines is coupled to the memory cells. A sense amplifier is positioned between the first block and the second block, and a plurality of electrical connections is made between the sense amplifier and the bit lines. A plurality of isolation transistors is electrically connected in series with the electrical connections, the isolation transistors being located within the first and second blocks and spaced from the sense amplifier block.
摘要翻译：存储器件具有位于第一块和第二块中的存储器单元阵列。存储单元以行和列排列。多个位线耦合到存储器单元，并且多个字线耦合到存储器单元。感测放大器位于第一块和第二块之间，并且在感测放大器和位线之间形成多个电连接。多个隔离晶体管与电连接串联电连接，隔离晶体管位于第一和第二块内并与读出放大器块间隔开。

16. 发明申请

WO2010042496A2 STACKED DEVICE REMAPPING AND REPAIR 审中-公开
标题翻译：堆叠设备重新包装和维修
公开(公告)号：WO2010042496A2
公开(公告)日：2010-04-15
申请号：PCT/US2009/059669
申请日：2009-10-06
申请人： MICRON TECHNOLOGY, INC. , KEETH, Brent , MARTIN, Chris G. , MANNING, Troy A. , JEDDELOH, Joe M. , COWLES, Timothy B. , REHMEYER, Jim , LABERGE, Paul A.
发明人： KEETH, Brent , MARTIN, Chris G. , MANNING, Troy A. , JEDDELOH, Joe M. , COWLES, Timothy B. , REHMEYER, Jim , LABERGE, Paul A.
IPC分类号： G11C8/04 , G11C8/06
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.
摘要翻译：各种实施例包括具有以堆叠方式布置的多个管芯的设备，系统和方法，其中有缺陷的单元可以被同一管芯或不同管芯上的备用单元替换。

17. 发明申请

WO2010030804A1 SIGNAL DELIVERY IN STACKED DEVICE 审中-公开
标题翻译：堆叠设备中的信号传递
公开(公告)号：WO2010030804A1
公开(公告)日：2010-03-18
申请号：PCT/US2009/056544
申请日：2009-09-10
申请人： MICRON TECHNOLOGY, INC. , KEETH, Brent , HIATT, Mark , LEE, Terry R. , TUTTLE, Mark , ADVANI, Rahul , SCHRECK, John F.
发明人： KEETH, Brent , HIATT, Mark , LEE, Terry R. , TUTTLE, Mark , ADVANI, Rahul , SCHRECK, John F.
IPC分类号： H01L23/12 , H01L23/48 , H01L21/60
CPC分类号： H01L25/0657 , H01L23/50 , H01L23/5385 , H01L23/66 , H01L25/0655 , H01L2223/6677 , H01L2224/0401 , H01L2224/06181 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06572 , H01L2924/01004 , H01L2924/15311 , Y10T29/49165
摘要： Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.
摘要翻译：一些实施例包括装置，系统和方法，其具有底座，第一管芯，第二管芯，第二管芯和第二管芯，第二管芯和第二管芯，第二管芯和第二管芯，被配置为在所述基座与所述第一和第二骰子中的至少一个之间传送信号。

18. 发明申请

WO2004001846A2 METHOD AND STRUCTURES FOR REDUCED PARASITIC CAPACITANCE IN INTEGRATED CIRCUIT METALLIZATIONS 审中-公开
标题翻译：集成电路金属化中降低PARASIIC电容的方法与结构
公开(公告)号：WO2004001846A2
公开(公告)日：2003-12-31
申请号：PCT/US2003/021029
申请日：2003-06-18
申请人： MICRON TECHNOLOGY, INC. , BATRA, Shubneesh , CHAINE, Michael, D. , KEETH, Brent , AKRAM, Salman , MANNING, Troy, A. , JOHNSON, Brian , MARTIN, Chris, G. , MERRITT, Todd, A. , SMITH, Eric, J.
发明人： BATRA, Shubneesh , CHAINE, Michael, D. , KEETH, Brent , AKRAM, Salman , MANNING, Troy, A. , JOHNSON, Brian , MARTIN, Chris, G. , MERRITT, Todd, A. , SMITH, Eric, J.
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels (M1, M2, M3, etc) is described. The method comprises forming a bond pad (20) at least partially exposed at the top surface of the integrated circuit, forming a metal pad (22) on the metal level (42) below the bond pad (20) and forming an underlying metal pad (26b) on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads (22, 26b) to the area of the bond pad (20) is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译：描述了一种降低具有三个或更多个金属水平（M1，M2，M3等）的集成电路中的寄生电容的方法。该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘（20），在接合焊盘（20）下方的金属层（42）上形成金属焊盘（22），并形成下面的金属焊盘（26b）在所述一个或多个下层金属层中的每一个上。在所示实施例中，下面的金属焊盘（22,26b）中的至少一个的面积与焊盘（20）的面积之比小于30％。寄生电容因此大大降低，信号传播速度提高。

19. 发明申请

WO2003069461A2 METHODS AND APPARATUS FOR ADAPTIVELY ADJUSTING A DATA RECEIVER 审中-公开
标题翻译：适应数据接收器的方法和设备
公开(公告)号：WO2003069461A2
公开(公告)日：2003-08-21
申请号：PCT/US2003/001944
申请日：2003-01-23
申请人： MICRON TECHNOLOGY, INC.
发明人： KEETH, Brent
IPC分类号： G06F5/06
CPC分类号： G11C7/1084 , G11C7/1078 , G11C7/1087 , G11C2207/2254
摘要： Offsets and timing skews in data signals captured in a data receiver are reduced by adaptively adjusting a transition threshold of the data receiver. A data corrector provides a set of adjustment vectors for adjusting the transition threshold of the data receiver. The data corrector uses differential clock signals and a reference voltage to generate the set of adjustment vectors to be provided to the data receivers. The data receiver is an improved receiver incorporating a trip point adjustor that receives the set of adjustment vectors from the data corrector to adjust its trip point relative to the reference voltage.
摘要翻译：通过自适应地调整数据接收器的转换阈值来减少在数据接收器中捕获的数据信号中的偏移和定时偏差。数据校正器提供用于调整数据接收器的转换阈值的一组调整向量。数据校正器使用差分时钟信号和参考电压来生成要提供给数据接收器的一组调整向量。数据接收机是一种改进的接收机，其包括一个跳变点调整器，该跳变点调节器从数据校正器接收一组调整向量，以调整其相对于参考电压的跳变点。

20. 发明申请

WO2002069132A3 IMPROVED HIGH SPEED DATA CAPTURE CIRCUIT FOR A DIGITAL DEVICE 审中-公开
公开(公告)号：WO2002069132A3
公开(公告)日：2002-09-06
申请号：PCT/US2002/002758
申请日：2002-02-01
申请人： MICRON TECHNOLOGY, INC.
发明人： KEETH, Brent , MARTIN, Chris, G.
IPC分类号： G06F7/00
摘要： A data capture circuit for an integrated circuit is disclosed which includes providing respective data paths between a latch and clock terminal and a latch and an associated data terminal, the length of each of the paths for a given latch device being approximately equal.

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