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11. 发明授权

US07051197B2 Tracing through reset 有权
标题翻译：跟踪通过重置
公开(公告)号：US07051197B2
公开(公告)日：2006-05-23
申请号：US10302082
申请日：2002-11-22
申请人： Manisha Agarwala , Lewis Nardini
发明人： Manisha Agarwala , Lewis Nardini
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.
摘要翻译：一种在数据处理器复位时跟踪数据处理器的方法。数据处理器复位信号复位数据处理器，跟踪收集硬件的一部分，不会复位跟踪收集硬件的剩余部分。数据处理器复位信号可以不是由应用程序所拥有或由调试器拥有的。跟踪收集硬件的部分不复位仅在调试器所拥有的数据处理器复位信号时发生。跟踪逻辑复位信号在不拥有时复位数据处理器和跟踪收集硬件。该跟踪逻辑复位信号仅在调试器拥有时复位数据处理器，并在应用程序拥有时重置跟踪收集硬件。

12. 发明授权

US07774758B2 Systems and methods for secure debugging and profiling of a computer system 有权
标题翻译：用于计算机系统安全调试和分析的系统和方法
公开(公告)号：US07774758B2
公开(公告)日：2010-08-10
申请号：US11383467
申请日：2006-05-15
申请人： Lewis Nardini , Manisha Agarwala , Oliver P. Sohm
发明人： Lewis Nardini , Manisha Agarwala , Oliver P. Sohm
IPC分类号： G06F9/44
CPC分类号： G06F11/3656 , G06F12/0897
摘要： The present disclosure describes methods and systems for secure debugging and profiling of a computer system. Some illustrative embodiments may include a system including a processor with a first processing stage and a first attribute register associated with the first processing stage, and including a memory system coupled to the processor. An instruction and an attribute value are stored within the memory system, wherein the instruction is loaded into the first processing stage and the attribute value is loaded into the first attribute register. Export of debug and profiling data from the first processing stage is disabled if the attribute value in the first attribute register indicates that the instruction in the first processing stage is a secure instruction, and further indicates that secure emulation is disabled.
摘要翻译：本公开描述了用于安全调试和分析计算机系统的方法和系统。一些说明性实施例可以包括包括具有第一处理级的处理器和与第一处理级相关联的第一属性寄存器的系统的系统，并且包括耦合到处理器的存储器系统。指令和属性值被存储在存储器系统内，其中指令被加载到第一处理级，并且属性值被加载到第一属性寄存器中。如果第一属性寄存器中的属性值指示第一处理阶段中的指令是安全指令，并且进一步指示安全仿真被禁用，则禁止从第一处理阶段导出调试和分析数据。

13. 发明授权

US07444504B2 Tracing through reset 有权
标题翻译：跟踪通过重置
公开(公告)号：US07444504B2
公开(公告)日：2008-10-28
申请号：US11820546
申请日：2007-06-20
申请人： Manisha Agarwala , Lewis Nardini
发明人： Manisha Agarwala , Lewis Nardini
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.
摘要翻译：一种在数据处理器复位时跟踪数据处理器的方法。数据处理器复位信号复位数据处理器，跟踪收集硬件的一部分，不会复位跟踪收集硬件的剩余部分。数据处理器复位信号可以不是由应用程序所拥有或由调试器拥有的。跟踪收集硬件的部分不复位仅在调试器所拥有的数据处理器复位信号时发生。跟踪逻辑复位信号在不拥有时复位数据处理器和跟踪收集硬件。该跟踪逻辑复位信号仅在调试器拥有时复位数据处理器，并在应用程序拥有时重置跟踪收集硬件。

14. 发明申请

US20080126871A1 Token-Based Trace System 有权
标题翻译：基于令牌的跟踪系统
公开(公告)号：US20080126871A1
公开(公告)日：2008-05-29
申请号：US11468114
申请日：2006-08-29
申请人： Lewis Nardini , Manisha Agarwala , Neil Common
发明人： Lewis Nardini , Manisha Agarwala , Neil Common
IPC分类号： G06F11/36
CPC分类号： G06F11/3636 , G06F11/3648
摘要： A system comprising a target hardware comprising multiple processor cores and an application. The system also comprises a host computer coupled to the target hardware by way of a connection and adapted to debug the application by receiving trace information via the connection. In determining which trace information to send via the connection, the target hardware gives priority to trace information generated by a primary processor core associated with a token over trace information generated by a secondary processor core not associated with the token. The token is associated with one of the multiple processor cores at a time.
摘要翻译：一种包括包括多个处理器核心和应用的目标硬件的系统。该系统还包括通过连接耦合到目标硬件的主计算机，并适于通过经由连接接收跟踪信息来调试应用程序。在确定通过连接发送的跟踪信息时，目标硬件优先于由与令牌相关联的主处理器核心生成的跟踪信息优先于由与令牌不相关联的辅助处理器核心生成的跟踪信息。令牌每次与多个处理器内核之一相关联。

15. 发明授权

US07606696B2 Programmable extended compression mask for dynamic trace 有权
标题翻译：可编程扩展压缩掩模，用于动态跟踪
公开(公告)号：US07606696B2
公开(公告)日：2009-10-20
申请号：US11566766
申请日：2006-12-05
申请人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
发明人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
IPC分类号： G06F9/455 , G06F11/273 , G06F11/34 , G06F3/00 , G06F13/12 , G01R13/28
CPC分类号： G06F11/3636 , G06F11/3476
摘要： This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least significant bytes of the current trace address that do not match the comparison address or are less significant than any section of the current trace address that does not match the comparison address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The comparison address is specified by a central processing unit via a memory mapped register write operation.
摘要翻译：本发明通过将当前跟踪地址的各个字节与存储的比较地址进行比较来提供跟踪地址压缩。只有当前跟踪地址中与比较地址不匹配或者比当前跟踪地址与比较地址不匹配的任何部分不太重要的最低有效字节被传送。这有时会减少需要传输的数据量。比较地址由中央处理单元通过存储器映射寄存器写入操作指定。

16. 发明授权

US07558987B2 Token-based trace system 有权
标题翻译：基于令牌的跟踪系统
公开(公告)号：US07558987B2
公开(公告)日：2009-07-07
申请号：US11468114
申请日：2006-08-29
申请人： Lewis Nardini , Manisha Agarwala , Neil Common
发明人： Lewis Nardini , Manisha Agarwala , Neil Common
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3648
摘要： A system comprising a target hardware comprising multiple processor cores and an application. The system also comprises a host computer coupled to the target hardware by way of a connection and adapted to debug the application by receiving trace information via the connection. In determining which trace information to send via the connection, the target hardware gives priority to trace information generated by a primary processor core associated with a token over trace information generated by a secondary processor core not associated with the token. The token is associated with one of the multiple processor cores at a time.
摘要翻译：一种包括包括多个处理器核心和应用的目标硬件的系统。该系统还包括通过连接耦合到目标硬件的主计算机，并适于通过经由连接接收跟踪信息来调试应用程序。在确定通过连接发送的跟踪信息时，目标硬件优先于由与令牌相关联的主处理器核心生成的跟踪信息优先于由与令牌不相关联的辅助处理器核心生成的跟踪信息。令牌每次与多个处理器内核之一相关联。

17. 发明授权

US07383367B2 Progressive extended compression mask for dynamic trace 有权
标题翻译：逐行扩展压缩掩码，用于动态跟踪
公开(公告)号：US07383367B2
公开(公告)日：2008-06-03
申请号：US11566757
申请日：2006-12-05
申请人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
发明人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
IPC分类号： G06F3/00 , G06F13/12 , G06F9/455 , G06R31/28
CPC分类号： G06F11/3636 , G06F11/3476
摘要： This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.
摘要翻译：本发明通过将当前跟踪地址的各个字节与存储的先前跟踪地址进行比较来提供跟踪地址压缩。只有当前跟踪地址中与存储的先前跟踪地址不匹配或者比当前跟踪地址中与存储的先前跟踪地址不匹配的任何部分不太重要的最低有效字节被传送。这有时会减少需要传输的数据量。如果存在完全不匹配，则可以使用当前跟踪地址更新先前的跟踪地址。

18. 发明申请

US20070294590A1 COMPRESSION SCHEME TO REDUCE THE BANDWIDTH REQUIREMENTS FOR CONTINUOUS TRACE STREAM ENCODING OF SYSTEM PERFORMANCE 审中-公开
标题翻译：压缩方案，以减少系统性能连续跟踪编码的带宽要求
公开(公告)号：US20070294590A1
公开(公告)日：2007-12-20
申请号：US11383697
申请日：2006-05-16
申请人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
发明人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： A system and method of counting event patterns in order to reduce the bandwidth of event data sent to a monitoring computer. The event patterns are output as one or more data packets indicating the event pattern and a number of occurrences of the pattern.
摘要翻译：计数事件模式的系统和方法，以减少发送到监控计算机的事件数据的带宽。事件模式作为一个或多个数据分组输出，指示事件模式和模式的出现次数。

19. 发明授权

US07047451B2 Tracing program counter addresses using native program counter format and instruction count format 有权
标题翻译：使用本地程序计数器格式和指令计数格式跟踪程序计数器地址
公开(公告)号：US07047451B2
公开(公告)日：2006-05-16
申请号：US10302025
申请日：2002-11-22
申请人： Manisha Agarwala , Bryan Thome , John M. Johnsen , Gary L. Swoboda , Lewis Nardini , Maria B. H. Gill
发明人： Manisha Agarwala , Bryan Thome , John M. Johnsen , Gary L. Swoboda , Lewis Nardini , Maria B. H. Gill
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program counter sync point. The program counter offset is sent as integral number of sections of a predetermined number of bits. Program counter sync points are transmitted often enough so that the program counter offset requires at most one less section than the program counter address.
摘要翻译：在数据处理器中跟踪程序计数器活动的方法周期性地发送包括当前程序计数器地址的程序计数器同步点。在同步点之间，程序计数器地址由相对于最后一个程序计数器同步点的程序计数器偏移指示。程序计数器偏移作为整数个预定位数的部分发送。程序计数器的同步点经常被传送到足够多的程序计数器偏移量至少比程序计数器地址少一个部分。

20. 发明授权

US07047270B2 Reporting a saturated counter value 有权
标题翻译：报告饱和计数器值
公开(公告)号：US07047270B2
公开(公告)日：2006-05-16
申请号：US10301897
申请日：2002-11-22
申请人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
发明人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
IPC分类号： G06F7/38
CPC分类号： G06F11/261
摘要： A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.
摘要翻译：饱和计数将接收的事件信号计数到第一预定数量。溢出计数器计数溢出到第二预定数量。当溢出计数达到第二个预定数量时，计数器指示溢出计数不为零并饱和，并以最大计数停止计数。可以通过寄存器读取操作读取计数器。第一预定位数和第二预定位数之和为8位的整数倍的总和。

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