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    • 16. 发明授权
    • Digital clock recovery loop
    • 数字时钟恢复回路
    • US06285261B1
    • 2001-09-04
    • US09610177
    • 2000-07-05
    • George E. PaxJames E. O'TooleDan M. Griffin
    • George E. PaxJames E. O'TooleDan M. Griffin
    • H03L100
    • H03L7/0895H03L7/0896H03L7/113H04B1/707H04L7/033
    • A method of using a phase lock loop to receive an oscillating input signal and produce an output signal, the phase lock loop comprising a plurality of flip-flops which are chained together, the plurality of flip-flops including a first flip-flop having a first output, including a second flip-flop having an input coupled to the first output and having a second output, and including a third flip-flop having an input coupled to the second output, the phase lock loop further comprising a control node, the method including using the flip-flops to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal; extracting a clock from an input digital signal; and performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.
    • 一种使用锁相环接收振荡输入信号并产生输出信号的方法,所述锁相环包括链接在一起的多个触发器,所述多个触发器包括具有第一触发器的第一触发器, 第一输出,包括具有耦合到第一输出并具有第二输出的输入的第二触发器,并且包括具有耦合到第二输出的输入的第三触发器,所述锁相环还包括控制节点, 方法,包括使用触发器来确定转变之间的时间间隔以执行输出信号相对于输入信号的频率比较; 从输入数字信号中提取时钟; 并执行相位控制和调节压控振荡器的控制节点上的电压。
    • 17. 发明授权
    • Digital clock recovery loop
    • 数字时钟恢复回路
    • US5774022A
    • 1998-06-30
    • US707220
    • 1996-08-29
    • Dan M. GriffinGeorge E. PaxJames E. O'Toole
    • Dan M. GriffinGeorge E. PaxJames E. O'Toole
    • H03L7/089H03L7/113H04B1/707H04L7/033H03L7/10
    • H03L7/113H03L7/0895H03L7/0896H04L7/033H04B1/707
    • A communications system including a clock recovery circuit that extracts a clock signal from incoming digital data, the clock recovery circuit including a voltage controlled oscillator having a control node and having an output producing an output wave having a frequency that varies in response to a voltage applied to the control node; charge pump and loop filter circuitry that controls the rate of change of the voltage on the control node of the voltage controlled oscillator; a start-up circuit that performs frequency detection and, in conjunction with the charge pump and loop filter circuitry, adjusts the voltage on the control node of the voltage controlled oscillator; and a state machine that performs phase detection and adjusts the voltage on the control node of the voltage controlled oscillator.
    • 一种通信系统,包括从输入数字数据中提取时钟信号的时钟恢复电路,所述时钟恢复电路包括具有控制节点的压控振荡器,并具有产生具有响应于施加的电压而变化的频率的输出波的输出 到控制节点; 电荷泵和环路滤波器电路,用于控制压控振荡器的控制节点上的电压变化率; 启动电路,执行频率检测,并结合电荷泵和环路滤波器电路调节压控振荡器的控制节点上的电压; 以及执行相位检测并调节压控振荡器的控制节点上的电压的状态机。