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11. 发明申请

US20100155710A1 FORMING ACTIVE CHANNEL REGIONS USING ENHANCED DROP-CAST PRINTING 有权
标题翻译：使用增强的压印打印形成活动通道区域
公开(公告)号：US20100155710A1
公开(公告)日：2010-06-24
申请号：US12604877
申请日：2009-10-23
申请人： Seonghoon Lee , Jung-Pyo Hong
发明人： Seonghoon Lee , Jung-Pyo Hong
IPC分类号： H01L51/30 , H01L51/40 , H01L51/10
CPC分类号： H01L51/0005 , H01L51/0007 , H01L51/0012 , H01L51/0094 , H01L51/0558 , Y02E10/549
摘要： An active region or channel for printed, organic or plastic electronics or polymer semiconductors, such as organic field-effect transistors (OFETs), is obtained by using an enhanced inkjet drop-cast printing technique. A two-liquid system is employed to achieve the direct growth of well-oriented organic crystals at the active region of channel. High-performance electrical properties exhibiting high carrier mobility and low threshold voltage are obtained due to the proper orientation of molecules in the grown crystal in a highest mobility direction, due to the absence of grain boundaries, and due to low trap densities. The hydrophobic-hydrophilic interactions between the liquids utilized, which results in the fabrication of low-cost and mass-producible printable electronic devices for applications in flexible displays, electronic signages, photovoltaic panels, membrane keyboards, radio frequency identification tags (RFIDs), electronic sensors, and integrated electronic circuits.
摘要翻译：通过使用增强型喷墨压铸技术获得印刷，有机或塑料电子或聚合物半导体（例如有机场效应晶体管（OFET））的有源区或沟道。采用双液体系统来实现通道活性区域中良好取向的有机晶体的直接生长。由于不存在晶界，并且由于陷阱密度低，由于在最高迁移率方向上生长晶体中分子的适当取向，因此获得了表现出高载流子迁移率和低阈值电压的高性能电性能。所使用的液体之间的疏水 - 亲水相互作用，这导致制造用于柔性显示器，电子标牌，光伏面板，膜键盘，射频识别标签（RFID），电子装置中的低成本和大量生产的可印刷电子装置传感器和集成电子电路。

12. 发明申请

US20060261867A1 Method and apparatus for timing domain crossing 有权
标题翻译：时域交叉的方法和装置
公开(公告)号：US20060261867A1
公开(公告)日：2006-11-23
申请号：US11495848
申请日：2006-07-28
申请人： Seonghoon Lee , J. Johnson
发明人： Seonghoon Lee , J. Johnson
IPC分类号： H03L7/00
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/4093
摘要： A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The sampled data signal is expanded to a plurality of expansion signals, which are held valid for a plurality of consecutive active clock cycles. A data order adjuster may re-order the plurality of expansion signals to a predetermined order. A timing generator samples a command signal with an internal clock in a second timing domain to generate a re-timing strobe. The re-timing strobe may be temporally positioned to be within the expansion data window and used to sample the plurality of expansion signals in the second timing domain. The timing domain crossing apparatus and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.
摘要翻译：公开了一种在定时域之间传送信号的定时域交叉装置和方法。接收机用第一定时域中的采样时钟对数据信号进行采样。采样的数据信号被扩展成多个扩展信号，这些扩展信号在多个连续的活动时钟周期中保持有效。数据顺序调整器可以将多个扩展信号重新排序到预定的顺序。定时发生器用第二定时域中的内部时钟对命令信号进行采样以产生重新定时选通。重新定时选通可以在时间上位于扩展数据窗口内，并用于在第二定时域中采样多个扩展信号。信号采样的定时域交叉装置和方法可以结合在半导体器件中，半导体器件可以制造在半导体晶片上并且被包括在电子系统中。

13. 发明申请

US20060034405A1 Method and apparatus for high-speed input sampling 有权
标题翻译：高速输入采样方法和装置
公开(公告)号：US20060034405A1
公开(公告)日：2006-02-16
申请号：US10918008
申请日：2004-08-12
申请人： Seonghoon Lee
发明人： Seonghoon Lee
IPC分类号： H04L7/00
CPC分类号： H03K5/135 , G11C27/02
摘要： A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock signal and generates a second sampled signal. The first and second sampled signals may be combined to determine the next signal sampler output. An evaluation may include asserting the output signal if the first and second sampled signals are asserted, negating the output signal if the first and second sampled signal are negated, and toggling the output signal if the first and second sampled signals are in opposite logic states. The signal sampler and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.
摘要翻译：公开了用于信号的高速输入采样的信号采样器和方法。第一采样器在时钟信号的上升沿采样数据信号并产生第一采样信号。第二采样器在反相时钟信号的下降沿采样数据信号，并产生第二采样信号。可以组合第一和第二采样信号以确定下一个信号采样器输出。如果第一和第二采样信号被断言，评估可以包括断言输出信号，如果第一和第二采样信号被否定则否定输出信号，如果第一和第二采样信号处于相反的逻辑状态，则转换输出信号。信号采样器和信号采样方法可以结合在半导体器件中，半导体器件可以制造在半导体晶片上并且被包括在电子系统中。

14. 发明授权

US08860008B2 Forming active channel regions using enhanced drop-cast printing 有权
标题翻译：使用增强型液滴打印形成活动通道区域
公开(公告)号：US08860008B2
公开(公告)日：2014-10-14
申请号：US12604877
申请日：2009-10-23
申请人： Seonghoon Lee , Jung-Pyo Hong
发明人： Seonghoon Lee , Jung-Pyo Hong
IPC分类号： H01L29/08
CPC分类号： H01L51/0005 , H01L51/0007 , H01L51/0012 , H01L51/0094 , H01L51/0558 , Y02E10/549
摘要： An active region or channel for printed, organic or plastic electronics or polymer semiconductors, such as organic field-effect transistors (OFETs), is obtained by using an enhanced inkjet drop-cast printing technique. A two-liquid system is employed to achieve the direct growth of well-oriented organic crystals at the active region of channel. High-performance electrical properties exhibiting high carrier mobility and low threshold voltage are obtained due to the proper orientation of molecules in the grown crystal in a highest mobility direction, due to the absence of grain boundaries, and due to low trap densities. The hydrophobic-hydrophilic interactions between the liquids utilized, which results in the fabrication of low-cost and mass-producible printable electronic devices for applications in flexible displays, electronic signages, photovoltaic panels, membrane keyboards, radio frequency identification tags (RFIDs), electronic sensors, and integrated electronic circuits.
摘要翻译：通过使用增强型喷墨压铸技术获得印刷，有机或塑料电子或聚合物半导体（例如有机场效应晶体管（OFET））的有源区或沟道。采用双液体系统来实现通道活性区域中良好取向的有机晶体的直接生长。由于不存在晶界，并且由于陷阱密度低，由于在最高迁移率方向上生长晶体中分子的适当取向，因此获得了表现出高载流子迁移率和低阈值电压的高性能电性能。所使用的液体之间的疏水 - 亲水相互作用，这导致制造用于柔性显示器，电子标牌，光伏面板，膜键盘，射频识别标签（RFID），电子装置中的低成本和大量生产的可印刷电子装置传感器和集成电子电路。

15. 发明授权

US07224639B2 Multi-phase clock signal generator and method having inherently unlimited frequency capability 有权
标题翻译：具有固有无限频率能力的多相时钟信号发生器和方法
公开(公告)号：US07224639B2
公开(公告)日：2007-05-29
申请号：US11432238
申请日：2006-05-10
申请人： Seonghoon Lee
发明人： Seonghoon Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/1072 , G11C7/222 , H03L7/0805 , H03L7/0812
摘要： A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay units. The remaining delay lines are each composed of different numbers of variable delay units to provide respective clock signals having different phases, but they do not include any of the fixed delay units. The first and a last delay line receive an input clock signal. Each of the remaining delay lines are coupled to an output of one of the fixed delay units depending on the number of variable delay units in the delay line so that the resulting clock signals have all been delayed the same number of fixed delay periods.
摘要翻译：延迟锁定环路包括若干延迟线，除了第一个延迟线之外，还包括提供固定延迟和可变延迟的至少一个可变延迟单元。第一延迟线由多个固定延迟单元组成，但不包括可变延迟单元。其余的延迟线分别由不同数目的可变延迟单元组成，以提供具有不同相位的相应时钟信号，但是它们不包括任何固定延迟单元。第一和最后一个延迟线接收输入时钟信号。每个剩余的延迟线根据延迟线中的可变延迟单元的数量耦合到固定延迟单元中的一个的输出，使得所得到的时钟信号全部被延迟相同数量的固定延迟周期。

16. 发明授权

US07106655B2 Multi-phase clock signal generator and method having inherently unlimited frequency capability 有权
标题翻译：具有固有无限频率能力的多相时钟信号发生器和方法
公开(公告)号：US07106655B2
公开(公告)日：2006-09-12
申请号：US11027376
申请日：2004-12-29
申请人： Seonghoon Lee
发明人： Seonghoon Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/1072 , G11C7/222 , H03L7/0805 , H03L7/0812
摘要： A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay units. The remaining delay lines are each composed of different numbers of variable delay units to provide respective clock signals having different phases, but they do not include any of the fixed delay units. The first and a last delay line receive an input clock signal. Each of the remaining delay lines are coupled to an output of one of the fixed delay units depending on the number of variable delay units in the delay line so that the resulting clock signals have all been delayed the same number of fixed delay periods.
摘要翻译：延迟锁定环路包括若干延迟线，除了第一个延迟线之外，还包括提供固定延迟和可变延迟的至少一个可变延迟单元。第一延迟线由多个固定延迟单元组成，但不包括可变延迟单元。其余的延迟线分别由不同数目的可变延迟单元组成，以提供具有不同相位的相应时钟信号，但是它们不包括任何固定延迟单元。第一和最后一个延迟线接收输入时钟信号。每个剩余的延迟线根据延迟线中的可变延迟单元的数量耦合到固定延迟单元中的一个的输出，使得所得到的时钟信号全部被延迟相同数量的固定延迟周期。

17. 发明授权

US07084680B2 Method and apparatus for timing domain crossing 失效
公开(公告)号：US07084680B2
公开(公告)日：2006-08-01
申请号：US10931397
申请日：2004-08-31
申请人： Seonghoon Lee , J. Brian Johnson
发明人： Seonghoon Lee , J. Brian Johnson
IPC分类号： H03L7/00
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/4093
摘要： A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock in a first timing domain. The sampled data signal is expanded to a plurality of expansion signals, which are held valid for a plurality of consecutive active clock cycles. A data order adjuster may re-order the plurality of expansion signals to a predetermined order. A timing generator samples a command signal with an internal clock in a second timing domain to generate a re-timing strobe. The re-timing strobe may be temporally positioned to be within the expansion data window and used to sample the plurality of expansion signals in the second timing domain. The timing domain crossing apparatus and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

18. 发明申请

US20060140024A1 MULTI-PHASE CLOCK SIGNAL GENERATOR AND METHOD HAVING INHERENTLY UNLIMITED FREQUENCY CAPABILITY 有权
标题翻译：多相时钟信号发生器及具有无限频率能力的方法
公开(公告)号：US20060140024A1
公开(公告)日：2006-06-29
申请号：US11027376
申请日：2004-12-29
申请人： Seonghoon Lee
发明人： Seonghoon Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1072 , G11C7/222 , H03L7/0805 , H03L7/0812
摘要： A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay units. The remaining delay lines are each composed of different numbers of variable delay units to provide respective clock signals having different phases, but they do not include any of the fixed delay units. The first and a last delay line receive an input clock signal. Each of the remaining delay lines are coupled to an output of one of the fixed delay units depending on the number of variable delay units in the delay line so that the resulting clock signals have all been delayed the same number of fixed delay periods.
摘要翻译：延迟锁定环路包括若干延迟线，除了第一个延迟线之外，还包括提供固定延迟和可变延迟的至少一个可变延迟单元。第一延迟线由多个固定延迟单元组成，但不包括可变延迟单元。其余的延迟线分别由不同数目的可变延迟单元组成，以提供具有不同相位的相应时钟信号，但是它们不包括任何固定延迟单元。第一和最后一个延迟线接收输入时钟信号。每个剩余的延迟线根据延迟线中的可变延迟单元的数量耦合到固定延迟单元中的一个的输出，使得所得到的时钟信号全部被延迟相同数量的固定延迟周期。

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