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11. 发明授权

US07416963B2 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07416963B2
公开(公告)日：2008-08-26
申请号：US11182055
申请日：2005-07-15
申请人： Mitsuo Umemoto , Yoshio Okayama , Kazumasa Tanida , Hiroshi Terao , Yoshihiko Nemoto
发明人： Mitsuo Umemoto , Yoshio Okayama , Kazumasa Tanida , Hiroshi Terao , Yoshihiko Nemoto
IPC分类号： H01L21/00 , H01L21/44 , H01L29/40 , H01L23/52 , H01L23/48
CPC分类号： H01L21/76898 , H01L2224/0231 , H01L2224/02372 , H01L2224/05548
摘要： This invention offers a manufacturing method to reduce a manufacturing cost of a semiconductor device having a through-hole electrode by simplifying a manufacturing process and to enhance yield of the semiconductor device. A first insulation film is formed on a top surface of a semiconductor substrate. A part of the first insulation film is etched to form an opening in which a part of the semiconductor substrate is exposed. Then a pad electrode is formed in the opening and on the first insulation film. A second insulation film is formed on a back surface of the semiconductor substrate. Then a via hole having an aperture larger than the opening is formed. And a third insulation film is formed in the via hole and on the second insulation film. The third insulation film on a bottom of the via hole is etched to expose the pad electrode. After that, a through-hole electrode and a wiring layer are formed in the via hole. Finally, the semiconductor substrate is cut and separated into a plurality of semiconductor dice.
摘要翻译：本发明提供了通过简化制造工艺并提高半导体器件的产量来降低具有通孔电极的半导体器件的制造成本的制造方法。第一绝缘膜形成在半导体衬底的顶表面上。蚀刻第一绝缘膜的一部分以形成半导体衬底的一部分露出的开口。然后在开口和第一绝缘膜上形成焊盘电极。第二绝缘膜形成在半导体衬底的背面上。然后形成具有比开口大的孔的通孔。并且在通孔和第二绝缘膜上形成第三绝缘膜。对通孔的底部的第三绝缘膜进行蚀刻以露出焊盘电极。之后，在通孔中形成通孔电极和布线层。最后，将半导体衬底切割并分离成多个半导体管芯。

12. 发明申请

US20060033168A1 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20060033168A1
公开(公告)日：2006-02-16
申请号：US11182055
申请日：2005-07-15
申请人： Mitsuo Umemoto , Yoshio Okayama , Kazumasa Tanida , Hiroshi Terao , Yoshihiko Nemoto
发明人： Mitsuo Umemoto , Yoshio Okayama , Kazumasa Tanida , Hiroshi Terao , Yoshihiko Nemoto
IPC分类号： H01L29/76
CPC分类号： H01L21/76898 , H01L2224/0231 , H01L2224/02372 , H01L2224/05548
摘要： This invention offers a manufacturing method to reduce a manufacturing cost of a semiconductor device having a through-hole electrode by simplifying a manufacturing process and to enhance yield of the semiconductor device. A first insulation film is formed on a top surface of a semiconductor substrate. A part of the first insulation film is etched to form an opening in which a part of the semiconductor substrate is exposed. Then a pad electrode is formed in the opening and on the first insulation film. A second insulation film is formed on a back surface of the semiconductor substrate. Then a via hole having an aperture larger than the opening is formed. And a third insulation film is formed in the via hole and on the second insulation film. The third insulation film on a bottom of the via hole is etched to expose the pad electrode. After that, a through-hole electrode and a wiring layer are formed in the via hole. Finally, the semiconductor substrate is cut and separated into a plurality of semiconductor dice.
摘要翻译：本发明提供了通过简化制造工艺并提高半导体器件的产量来降低具有通孔电极的半导体器件的制造成本的制造方法。第一绝缘膜形成在半导体衬底的顶表面上。蚀刻第一绝缘膜的一部分以形成半导体衬底的一部分露出的开口。然后在开口和第一绝缘膜上形成焊盘电极。第二绝缘膜形成在半导体衬底的背面上。然后形成具有比开口大的孔的通孔。并且在通孔和第二绝缘膜上形成第三绝缘膜。对通孔的底部的第三绝缘膜进行蚀刻以露出焊盘电极。之后，在通孔中形成通孔电极和布线层。最后，将半导体衬底切割并分离成多个半导体管芯。

13. 发明授权

US07256497B2 Semiconductor device with a barrier layer and a metal layer 有权
标题翻译：具有阻挡层和金属层的半导体器件
公开(公告)号：US07256497B2
公开(公告)日：2007-08-14
申请号：US11054603
申请日：2005-02-10
申请人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
发明人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
IPC分类号： H01L29/74 , H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L27/14683 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05026 , H01L2224/05124 , H01L2224/05181 , H01L2224/05548 , H01L2224/05569 , H01L2224/05624 , H01L2224/05647 , H01L2224/16 , H01L2924/01078 , H01L2924/04941 , H01L2924/3025 , H01L2924/00014
摘要： This invention provides a semiconductor device that can minimize deterioration of electric characteristics of the semiconductor device while minimizing the amount of etching required. In the semiconductor device of the invention, a pad electrode layer formed of a first barrier layer and an aluminum layer laminated thereon is formed on a top surface of a semiconductor substrate. A supporting substrate is further attached on the top surface of the semiconductor substrate. A second barrier layer is formed on a back surface of the semiconductor substrate and in a via hole formed from the back surface of the semiconductor substrate to the first barrier layer. Furthermore, a wiring layer is formed in the via hole so as to completely fill the via hole or so as not to completely fill the via hole. A ball-shaped terminal is formed on the wiring layer.
摘要翻译：本发明提供一种能够最小化所需蚀刻量的半导体器件的电特性的劣化最小化的半导体器件。在本发明的半导体器件中，在半导体衬底的顶表面上形成由第一阻挡层和层叠在其上的铝层形成的焊盘电极层。支撑衬底进一步附着在半导体衬底的顶表面上。第二阻挡层形成在半导体衬底的背面和从半导体衬底的背面形成到第一阻挡层的通孔中。此外，在通孔中形成布线层，以便完全填充通孔或不完全填充通孔。在布线层上形成球状端子。

14. 发明申请

US20050196957A1 Semiconductor device manufacturing method thereof 有权
标题翻译：半导体装置的制造方法
公开(公告)号：US20050196957A1
公开(公告)日：2005-09-08
申请号：US11057413
申请日：2005-02-15
申请人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
发明人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76898 , H01L2224/02372 , H01L2224/05548
摘要： This invention provides an etching method for preventing deformation of an opening without extremely lowering productivity. This invention has a process for bonding a supporting board on a front surface of a semiconductor substrate to cover a pad electrode formed on the semiconductor substrate with a silicon oxide film interposed therebetween, a process for forming a via hole from a back surface of the semiconductor substrate to a surface of the pad electrode, a process for forming a first opening in the semiconductor substrate to a position where the silicon oxide film is not exposed with using etching gas containing SF6 and O2 at least, and a process for forming a second opening in the semiconductor substrate to a position where the silicon oxide film is exposed with using etching gas containing C4F8 and SF6 at least.
摘要翻译：本发明提供一种用于防止开口变形而不降低生产率的蚀刻方法。本发明具有将半导体衬底的前表面上的支撑板接合以覆盖形成在半导体衬底上的衬垫电极的工艺，其中介于其间的氧化硅膜，用于从半导体的背面形成通孔的工艺衬底到焊盘电极的表面，用于在半导体衬底中形成第一开口到使用含有SF 6和O 3的蚀刻气体不暴露氧化硅膜的位置的工艺， 2＆gt;中所述的方法，以及在所述半导体衬底中形成第二开口的工艺，其中所述氧化硅膜暴露于使用含有C 4 C 8的蚀刻气体的位置处， / SUB>和SF <6>至少。

15. 发明申请

US20050269704A1 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20050269704A1
公开(公告)日：2005-12-08
申请号：US11054603
申请日：2005-02-10
申请人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
发明人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/12 , H01L23/48 , H01L29/74 , H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L27/14683 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05026 , H01L2224/05124 , H01L2224/05181 , H01L2224/05548 , H01L2224/05569 , H01L2224/05624 , H01L2224/05647 , H01L2224/16 , H01L2924/01078 , H01L2924/04941 , H01L2924/3025 , H01L2924/00014
摘要： This invention provides a semiconductor device and a manufacturing method thereof which can minimize deterioration of electric characteristics of the semiconductor device without increasing an etching process. In the semiconductor device of the invention, a pad electrode layer formed of a first barrier layer and an aluminum layer laminated thereon is formed on a top surface of a semiconductor substrate. A supporting substrate is further attached on the top surface of the semiconductor substrate. A second barrier layer is formed on a back surface of the semiconductor substrate and in a via hole formed from the back surface of the semiconductor substrate to the first barrier layer. Furthermore, a re-distribution layer is formed in the via hole so as to completely fill the via hole or so as not to completely fill the via hole. A ball-shaped terminal is formed on the re-distribution layer.
摘要翻译：本发明提供一种半导体器件及其制造方法，其可以在不增加蚀刻工艺的情况下最小化半导体器件的电特性的劣化。在本发明的半导体器件中，在半导体衬底的顶表面上形成由第一阻挡层和层叠在其上的铝层形成的焊盘电极层。支撑衬底进一步附着在半导体衬底的顶表面上。第二阻挡层形成在半导体衬底的背面和从半导体衬底的背面形成到第一阻挡层的通孔中。此外，在通孔中形成再分布层，以便完全填充通孔或不完全填充通孔。在再分配层上形成有球状的端子。

16. 发明授权

US08278213B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08278213B2
公开(公告)日：2012-10-02
申请号：US11054616
申请日：2005-02-10
申请人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
发明人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L24/10 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/13 , H01L27/14636 , H01L27/1469 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05147 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/00 , H01L2924/00014
摘要： This invention improves reliability of a semiconductor device and a manufacturing method thereof. A glass substrate is bonded on a surface of a silicon wafer formed with pad electrodes. Next, via holes are formed from a back surface of the silicon wafer to pad electrodes, and a groove is formed extending along a center line of a dicing line and penetrating the silicon wafer from its back surface. After then, in processes including heating treatment, cushioning pads, wirings, a solder mask, and solder balls are formed on the back surface of the silicon wafer. Finally, the silicon wafer bolstered by the glass substrate is separated into individual silicon dice by dicing.
摘要翻译：本发明提高了半导体器件的可靠性及其制造方法。在形成有焊盘电极的硅晶片的表面上接合玻璃基板。接下来，从硅晶片的背面到焊盘电极形成通孔，沿着切割线的中心线延伸并从其背面穿透硅晶片。之后，在硅晶片的背面形成有包括加热处理的工艺，缓冲垫，布线，焊接掩模和焊球。最后，由玻璃基板支撑的硅晶片通过切割分离成单独的硅片。

17. 发明申请

US20070254475A1 Semiconductor device with a barrier layer and a metal layer 有权
标题翻译：具有阻挡层和金属层的半导体器件
公开(公告)号：US20070254475A1
公开(公告)日：2007-11-01
申请号：US11822262
申请日：2007-07-03
申请人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
发明人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L27/14683 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05026 , H01L2224/05124 , H01L2224/05181 , H01L2224/05548 , H01L2224/05569 , H01L2224/05624 , H01L2224/05647 , H01L2224/16 , H01L2924/01078 , H01L2924/04941 , H01L2924/3025 , H01L2924/00014
摘要： This invention provides a semiconductor device and a manufacturing method thereof which can minimize deterioration of electric characteristics of the semiconductor device without increasing an etching process. In the semiconductor device of the invention, a pad electrode layer formed of a first barrier layer and an aluminum layer laminated thereon is formed on a top surface of a semiconductor substrate. A supporting substrate is further attached on the top surface of the semiconductor substrate. A second barrier layer is formed on a back surface of the semiconductor substrate and in a via hole formed from the back surface of the semiconductor substrate to the first barrier layer. Furthermore, a re-distribution layer is formed in the via hole so as to completely fill the via hole or so as not to completely fill the via hole. A ball-shaped terminal is formed on the re-distribution layer.
摘要翻译：本发明提供一种半导体器件及其制造方法，其可以在不增加蚀刻工艺的情况下最小化半导体器件的电特性的劣化。在本发明的半导体器件中，在半导体衬底的顶表面上形成由第一阻挡层和层叠在其上的铝层形成的焊盘电极层。支撑衬底进一步附着在半导体衬底的顶表面上。第二阻挡层形成在半导体衬底的背面和从半导体衬底的背面形成到第一阻挡层的通孔中。此外，在通孔中形成再分布层，以便完全填充通孔或不完全填充通孔。在再分配层上形成有球状的端子。

18. 发明授权

US07241679B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07241679B2
公开(公告)日：2007-07-10
申请号：US11057413
申请日：2005-02-15
申请人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
发明人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L2224/02372 , H01L2224/05548
摘要： This invention provides an etching method for preventing deformation of an opening without extremely lowering productivity. This invention has a process for bonding a supporting board on a front surface of a semiconductor substrate to cover a pad electrode formed on the semiconductor substrate with a silicon oxide film interposed therebetween, a process for forming a via hole from a back surface of the semiconductor substrate to a surface of the pad electrode, a process for forming a first opening in the semiconductor substrate to a position where the silicon oxide film is not exposed with using etching gas containing SF6 and O2 at least, and a process for forming a second opening in the semiconductor substrate to a position where the silicon oxide film is exposed with using etching gas containing C4F8 and SF6 at least.
摘要翻译：本发明提供一种用于防止开口变形而不降低生产率的蚀刻方法。本发明具有将半导体衬底的前表面上的支撑板接合以覆盖形成在半导体衬底上的衬垫电极的工艺，其中介于其间的氧化硅膜，用于从半导体的背面形成通孔的工艺衬底到焊盘电极的表面，用于在半导体衬底中形成第一开口到使用含有SF 6和O 3的蚀刻气体不暴露氧化硅膜的位置的工艺， 2＆gt;中所述的方法，以及在所述半导体衬底中形成第二开口的工艺，其中所述氧化硅膜暴露于使用含有C 4 C 8的蚀刻气体的位置处， / SUB>和SF <6 。

19. 发明申请

US20050194670A1 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20050194670A1
公开(公告)日：2005-09-08
申请号：US11054616
申请日：2005-02-10
申请人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
发明人： Koujiro Kameyama , Akira Suzuki , Yoshio Okayama
IPC分类号： H01L23/52 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L21/84 , H01L23/02 , H01L23/12 , H01L23/31 , H01L23/48 , H01L23/485 , H01L23/522
CPC分类号： H01L24/10 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L24/13 , H01L27/14636 , H01L27/1469 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05147 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/00 , H01L2924/00014
摘要： This invention improves reliability of a semiconductor device and a manufacturing method thereof. A glass substrate is bonded on a surface of a silicon wafer formed with pad electrodes. Next, via holes are formed from a back surface of the silicon wafer to pad electrodes, and a groove is formed extending along a center line of a dicing line and penetrating the silicon wafer from its back surface. After then, in processes including heating treatment, cushioning pads, wirings, a solder mask, and solder balls are formed on the back surface of the silicon wafer. Finally, the silicon wafer bolstered by the glass substrate is separated into individual silicon dice by dicing.
摘要翻译：本发明提高了半导体器件的可靠性及其制造方法。在形成有焊盘电极的硅晶片的表面上接合玻璃基板。接下来，从硅晶片的背面到焊盘电极形成通孔，沿着切割线的中心线延伸并从其背面穿透硅晶片。之后，在硅晶片的背面形成有包括加热处理的工艺，缓冲垫，布线，焊接掩模和焊球。最后，由玻璃基板支撑的硅晶片通过切割分离成单独的硅片。

20. 发明授权

US08338946B2 Semiconductor module, method of manufacturing semiconductor module, and mobile device 有权
标题翻译：半导体模块，制造半导体模块的方法和移动设备
公开(公告)号：US08338946B2
公开(公告)日：2012-12-25
申请号：US12961171
申请日：2010-12-06
申请人： Yasuyuki Yanase , Yoshio Okayama , Kiyoshi Shibata , Yasunori Inoue , Hideki Mizuhara , Ryosuke Usui , Tetsuya Yamamoto , Masurao Yoshii
发明人： Yasuyuki Yanase , Yoshio Okayama , Kiyoshi Shibata , Yasunori Inoue , Hideki Mizuhara , Ryosuke Usui , Tetsuya Yamamoto , Masurao Yoshii
IPC分类号： H01L23/48 , H01L29/40
CPC分类号： H01L24/11 , H01L23/3114 , H01L23/525 , H01L24/94 , H01L2221/6834 , H01L2221/68359 , H01L2224/0231 , H01L2224/02319 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05647 , H01L2224/1132 , H01L2224/114 , H01L2224/116 , H01L2224/131 , H01L2224/13147 , H01L2224/274 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01059 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/351 , H01L2224/13099 , H01L2924/00 , H01L2924/00014
摘要： An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.
摘要翻译：在半导体模块中的半导体衬底的安装表面（特别是其外周）上形成用于半导体器件的电极。为了确保电极之间的大间隙，在电极上形成绝缘层。还形成有穿过绝缘层并连接到电极的多个凸块，以及与凸块一体形成的重新布线图案。重新布线图案包括凸起区域和与凸起区域相邻延伸的布线区域。绝缘层形成为具有在凸起之间的间隔中的凹的上表面，并且重新布线图案的布线区域形成为适合该上表面。重布线图案的布线区域相对于重新布线图案的凸起区域形成为朝向半导体基板压下。

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