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11. 发明授权

US06910056B1 Method and apparatus for implementing a multi-step pseudo random sequence generator 有权
标题翻译：用于实现多步伪随机序列发生器的方法和装置
公开(公告)号：US06910056B1
公开(公告)日：2005-06-21
申请号：US09924675
申请日：2001-08-08
申请人： Volker Mauer
发明人： Volker Mauer
IPC分类号： G06F1/02 , G06F7/58
CPC分类号： G06F7/584 , G06F2207/583
摘要： A method for implementing a pseudo random sequence (PRS) generator is disclosed. Relationships between outputs of flip-flops of an initial model PRS generator at a current time step t with the outputs of the flip-flops at a time step t-n is determined, where n is a number of coefficients to be generated per time step. Flip-flops in the multi-step PRS generator are coupled in response to the relationships between the outputs of the flip-flops at the current time step t with the output of the flip-flops at the time step t-n.
摘要翻译：公开了一种用于实现伪随机序列（PRS）生成器的方法。确定在当前时间步长t的初始模型PRS发生器的触发器的输出与时间步长t-n处触发器的输出之间的关系，其中n是每个时间步长将要产生的系数的数量。多级PRS发生器中的触发器响应于在当前时间步长t的触发器的输出与时间步长t-n的触发器的输出之间的关系而耦合。

12. 发明授权

US07586995B1 Peak windowing for crest factor reduction 有权
标题翻译：峰值窗口降低波峰因数
公开(公告)号：US07586995B1
公开(公告)日：2009-09-08
申请号：US11109536
申请日：2005-04-18
申请人： Volker Mauer , Kulwinder Dhanoa , Paul Metzgen
发明人： Volker Mauer , Kulwinder Dhanoa , Paul Metzgen
IPC分类号： H04L25/49
CPC分类号： H04L27/3411
摘要： In order to reduce the crest factor of a signal for power amplification, a windowing function is applied. The windowing function that is applied is a triangular windowing function. The use of this function produces good results when those results are measured in terms of their effect on a transmitted signal in a WCDMA communications system. The filter for performing the triangular windowing function receives the signal, and applies it to a first delay element. The output from the first delay element is applied to a second delay element. An adder forms a weighted sum of the received signal and the signals at the outputs of the first delay element and the second delay element. A first accumulator is connected to receive an input from the adder and provides a first accumulator output, while a second accumulator is connected to receive an input from the first accumulator output and provides a second accumulator output.
摘要翻译：为了降低用于功率放大的信号的波峰因数，应用窗口功能。应用的窗口功能是三角窗口功能。当这些结果在其对WCDMA通信系统中的发射信号的影响方面测量时，使用该功能产生良好的结果。用于执行三角窗函数的滤波器接收信号，并将其施加到第一延迟元件。来自第一延迟元件的输出被施加到第二延迟元件。加法器形成接收信号和第一延迟元件和第二延迟元件的输出处的信号的加权和。连接第一累加器以从加法器接收输入并提供第一累加器输出，而第二累加器被连接以接收来自第一累加器输出的输入并提供第二累加器输出。

13. 发明授权

US06944577B1 Method and apparatus for extracting data from an oversampled bit stream 失效
标题翻译：用于从过采样比特流中提取数据的方法和装置
公开(公告)号：US06944577B1
公开(公告)日：2005-09-13
申请号：US10728228
申请日：2003-12-03
申请人： Volker Mauer , James Tyson
发明人： Volker Mauer , James Tyson
IPC分类号： G06F15/00
CPC分类号： H04L7/0338 , H04L7/007
摘要： Apparatus and method extract data from a data stream. The method includes oversampling the data stream, performing first processing on adjacent bits of the oversampled data stream, performing second processing the results of the first processing, comparing the results of the second processing, and selecting an alignment of data based on the comparison. The method can be efficiently implemented using accumulators, delay elements, and XOR elements. In this manner, data may be extracted from the data stream despite a varying or unknown phase or duty cycle, or in the presence of jitter.
摘要翻译：设备和方法从数据流中提取数据。该方法包括对数据流进行过采样，对过采样数据流的相邻位执行第一处理，对第一处理的结果进行第二处理，比较第二处理的结果，以及基于比较选择数据的对齐。可以使用累加器，延迟元件和XOR元件来有效地实现该方法。以这种方式，尽管变化或未知的相位或占空比，或者在存在抖动的情况下，也可以从数据流中提取数据。

14. 发明授权

US08914716B2 Resource sharing in decoder architectures 有权
标题翻译：解码器架构中的资源共享
公开(公告)号：US08914716B2
公开(公告)日：2014-12-16
申请号：US12341091
申请日：2008-12-22
申请人： Volker Mauer , Zhengjun Pan
发明人： Volker Mauer , Zhengjun Pan
IPC分类号： H03M13/03 , H03M13/39 , H03M13/00
CPC分类号： H03M13/3922 , H03M13/3972 , H03M13/6583
摘要： A state metric calculator for calculating state metrics of stages in a trellis of a sequence estimation technique is described. The calculator has a processing path containing operations needed for calculating a state metric of a trellis stage from state metrics of an earlier trellis stage. One or more data stores are located in the processing path to divide the path into separate sections. The sections can then operate on the production of different state metrics to one another in, if desired, the same clock cycle.
摘要翻译：描述了用于计算序列估计技术的网格中的阶段的状态度量的状态度量计算器。计算器具有处理路径，该处理路径包含从早期格状阶段的状态度量计算网格阶段的状态度量所需的操作。一个或多个数据存储位于处理路径中，以将路径划分成单独的部分。然后，如果需要，这些部分可以在不同的状态度量的产生上相同操作相同的时钟周期。

15. 发明授权

US08583715B1 Configuring a CIC filter in a programmable integrated circuit device 有权
标题翻译：在可编程集成电路设备中配置CIC滤波器
公开(公告)号：US08583715B1
公开(公告)日：2013-11-12
申请号：US11934149
申请日：2007-11-02
申请人： Zhengjun Pan , Volker Mauer
发明人： Zhengjun Pan , Volker Mauer
IPC分类号： G06F17/10
CPC分类号： H03H17/0671 , H03H2017/0297 , H03K19/17728
摘要： A programmable integrated circuit device can be configured as a cascaded integrator-comb (CIC) filter. In order to take advantage of Hogenauer pruning to configure the CIC filter efficiently, a software tool for configuring the device can be provided in which the Fj terms for Hogenauer pruning have been calculated in advance for all possible user parameters supported by the tool. To configure a CIC filter, the user enters the parameters in the tool, which then looks up the Fj terms corresponding to those parameters and completes the calculation of the Bj terms for Hogenauer pruning. Because the calculation of the Fj terms is the most time-consuming step in calculating of the Bj terms, pre-calculation of the Fj terms, which can be done just once by the provider of the tool, allows end users to calculate the Bj terms in reasonable periods of time, making Hogenauer pruning available to end users.
摘要翻译：可编程集成电路器件可以被配置为级联积分梳（CIC）滤波器。为了利用Hogenauer修剪来有效地配置CIC过滤器，可以提供用于配置设备的软件工具，其中Hogenauer修剪的Fj项已经被预先计算出用于该工具支持的所有可能的用户参数。要配置CIC过滤器，用户在工具中输入参数，然后查找与这些参数对应的Fj项，并完成Hogenauer修剪的Bj项的计算。因为Fj项的计算是计算Bj项最耗时的步骤，所以可以由工具提供者仅仅完成一次的Fj项的预计算，允许最终用户计算Bj项在合理的时间内，使Hogenauer修剪可用于最终用户。

16. 发明授权

US07039091B1 Method and apparatus for implementing a two dimensional correlator 失效
标题翻译：用于实现二维相关器的方法和装置
公开(公告)号：US07039091B1
公开(公告)日：2006-05-02
申请号：US09892051
申请日：2001-06-26
申请人： Volker Mauer
发明人： Volker Mauer
IPC分类号： H04B7/216
CPC分类号： H04B1/7077 , H04B1/70752 , H04B1/70775 , H04B1/7095
摘要： A method for managing a code sequence according to a first embodiment of the present invention is disclosed. Sets of n contiguous sample values that include sample values in a plurality of sample sequences are accessed. Sets of n contiguous coefficients are accessed. The sample values in each of the plurality of sets of sample values that are accessed are processed in parallel with corresponding coefficients that are accessed. Each of the plurality of sets of sample values are processed during a different time step.
摘要翻译：公开了一种用于管理根据本发明的第一实施例的代码序列的方法。访问包括多个采样序列中的采样值的n个连续采样值的集合。访问n个连续系数的集合。被访问的多组采样值的每一组中的采样值与被访问的相应系数并行处理。多个采样值集合中的每一个在不同的时间步长期间被处理。

17. 发明授权

US08959136B1 Matrix operations in an integrated circuit device 有权
标题翻译：集成电路器件中的矩阵运算
公开(公告)号：US08959136B1
公开(公告)日：2015-02-17
申请号：US13466805
申请日：2012-05-08
申请人： Colman C. Cheung , Steven Perry , Volker Mauer , Mark Jervis
发明人： Colman C. Cheung , Steven Perry , Volker Mauer , Mark Jervis
IPC分类号： G06F17/16
CPC分类号： G06F17/16 , G06F17/12
摘要： Efficient matrix operations circuitry is based on combining a matrix decomposition and a forward substitution operations to share the same processing overhead. A dual multiplier circuit selectively applies complex multiplication operations to a first and second input vectors for computing a conjugate dot product vector or a non-conjugate dot product vector. The conjugate dot product vector corresponds to the matrix decomposition operation for triangulating an input matrix to generate an element of a triangulated matrix. The non-conjugate dot product vector corresponds to a forward substitution operation for determining an element of a forward substitution vector from the triangulated matrix.
摘要翻译：有效的矩阵运算电路基于组合矩阵分解和前向替换操作以共享相同的处理开销。双乘法器电路选择性地将复乘法运算应用于第一和第二输入向量，用于计算共轭点积矢量或非共轭点乘积矢量。共轭点乘积向量对应于用于三角测量输入矩阵以生成三角矩阵的元素的矩阵分解操作。非共轭点积矢量对应于用于确定来自三角测量矩阵的正向替换矢量的元素的正向替换操作。

18. 发明授权

US08578255B1 Priming of metrics used by convolutional decoders 有权
标题翻译：卷积解码器使用的度量的引导
公开(公告)号：US08578255B1
公开(公告)日：2013-11-05
申请号：US12339482
申请日：2008-12-19
申请人： Zhengjun Pan , Volker Mauer
发明人： Zhengjun Pan , Volker Mauer
IPC分类号： H03M13/03 , H03M13/00
CPC分类号： H03M13/3723 , H03M13/3905 , H03M13/3972
摘要： A sequence estimator is described. In one embodiment, the sequence estimator includes a plurality of maximum a posteriori probability (MAP) decoding engines each arranged to process a series of windows of a transmitted signal where state metrics produced for an end of one window by one decoding engine are re-used for the initialization of a state metric calculation process performed by another decoding engine on another window of the signal.
摘要翻译：描述序列估计器。在一个实施例中，序列估计器包括多个最大后验概率（MAP）解码引擎，每个最大后验概率（MAP）解码引擎被配置为处理发送信号的一系列窗口，其中由一个解码引擎为一个窗口的结尾产生的状态度量被重新使用用于初始化另一解码引擎在另一个信号窗口上执行的状态度量计算处理。

19. 发明授权

US08572456B1 Avoiding interleaver memory conflicts 有权
标题翻译：避免交织器内存冲突
公开(公告)号：US08572456B1
公开(公告)日：2013-10-29
申请号：US12470959
申请日：2009-05-22
申请人： Zhengjun Pan , Volker Mauer
发明人： Zhengjun Pan , Volker Mauer
IPC分类号： H03M13/00
CPC分类号： H03M13/2775
摘要： Interleaving and deinterleaving schemes for operating in parallel on sections of a data block to load memories with respective segments of a reordered version of the block, in a manner which can avoid memory conflicts.
摘要翻译：在数据块的各个部分上并行操作的交错和解交织方案，以能够避免存储器冲突的方式加载具有块的重新排版版本的各个段的存储器。

20. 发明授权

US08543634B1 Specialized processing block for programmable integrated circuit device 有权
标题翻译：可编程集成电路器件专用处理块
公开(公告)号：US08543634B1
公开(公告)日：2013-09-24
申请号：US13435133
申请日：2012-03-30
申请人： Lei Xu , Volker Mauer , Steven Perry
发明人： Lei Xu , Volker Mauer , Steven Perry
IPC分类号： G06F15/00
CPC分类号： G06F7/552 , G06F2207/5523
摘要： A specialized processing block such as a DSP block may be enhanced by including direct connections that allow the block output to be directly connected to either the multiplier inputs or the adder inputs of another such block. A programmable integrated circuit device may includes a plurality of such specialized processing blocks. The specialized processing block includes a multiplier having two multiplicand inputs and a product output, an adder having as one adder input the product output of the multiplier, and having a second adder input and an adder output, a direct-connect output of the adder output to a first other one of the specialized processing block, and a direct-connect input from a second other one of the specialized processing block. The direct-connect input connects a direct-connect output of that second other one of the specialized processing block to a first one of the multiplicand inputs.
摘要翻译：可以通过包括允许块输出直接连接到另一个这样的块的乘法器输入或加法器输入的直接连接来增强诸如DSP块的专门处理块。可编程集成电路设备可以包括多个这样的专用处理块。专用处理块包括具有两个被乘数输入和乘积输出的乘法器，具有一个加法器的加法器输入乘法器的乘积输出，并具有第二加法器输入和加法器输出，加法器输出的直接连接输出到专用处理块中的第一另一个，以及来自专门处理块中的另一个的直接连接输入。直接连接输入将专用处理块中另外另一个的直接连接输出连接到被乘数输入中的第一个。

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