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11. 外观设计

USD536297S1 Pontoon 有权
公开(公告)号：USD536297S1
公开(公告)日：2007-02-06
申请号：US29241473
申请日：2005-10-28
申请人： Yuji Awashima , Kentaro Watanabe , Kazuhiko Tsunoo
设计人： Yuji Awashima , Kentaro Watanabe , Kazuhiko Tsunoo

12. 发明授权

US06950341B2 Semiconductor memory device having plural sense amplifiers 有权
标题翻译：具有多个读出放大器的半导体存储器件
公开(公告)号：US06950341B2
公开(公告)日：2005-09-27
申请号：US10119840
申请日：2002-04-11
申请人： Yoshinori Takano , Kentaro Watanabe
发明人： Yoshinori Takano , Kentaro Watanabe
IPC分类号： G11C7/06 , G11C16/28 , G11C16/06 , G11C7/00
CPC分类号： G11C16/28
摘要： A semiconductor memory device is disclosed which includes an array of memory cells for storing data depending on whether current pull-in is present or absent or alternatively whether it is large or small, a plurality of sense lines with read data of the memory cell array transferred thereto, a reference sense line for common use in data sensing at the plurality of sense lines while being given a reference voltage for the data sense, and a sense amplifier array having a plurality of sense amplifiers for amplifying a difference voltage between the plurality of sense lines and the reference sense line to thereby determine read data.
摘要翻译：公开了一种半导体存储器件，其包括用于根据当前引入是存在还是不存在而存储数据的存储器单元阵列，或者替代地是大还是小，存储单元阵列的读数据传输的多条感测线在给定用于数据检测的参考电压的同时，在多个感测线上的数据感测中共同使用的参考感测线，以及具有用于放大多个感测之间的差分电压的多个读出放大器的读出放大器阵列线和参考感测线，从而确定读取数据。

13. 发明授权

US08833334B2 Oil pump apparatus 有权
标题翻译：油泵设备
公开(公告)号：US08833334B2
公开(公告)日：2014-09-16
申请号：US13885180
申请日：2011-11-17
申请人： Kentaro Watanabe , Motoyasu Yamamori , Ryouichi Takahata , Kazuya Ando , Naomasa Mukaide
发明人： Kentaro Watanabe , Motoyasu Yamamori , Ryouichi Takahata , Kazuya Ando , Naomasa Mukaide
IPC分类号： F01M1/02 , F04C11/00 , F01C21/10 , F04C2/10 , F04C14/26 , F04C15/06 , F04C15/00 , F16N13/06 , F01M1/12
CPC分类号： F01M1/02 , F01C21/108 , F01M2001/0215 , F01M2001/123 , F04C2/102 , F04C11/001 , F04C11/008 , F04C14/265 , F04C15/0026 , F04C15/06 , F04C2230/60 , F16N2013/063
摘要： An oil pump apparatus in which an electrical pump can be easily disposed is provided. A mechanical pump including: an inner gear which is configured to be driven by an engine; and an outer gear which is configured to mesh with the inner gear, and an electrical pump including: an outer gear which is configured to be driven by a motor section; and an inner gear which is configured to mesh with the outer gear are installed adjacent to each other in the axial direction in a pump installation space of a pump housing having suction ports and ejection ports. A blocking plate which is configured to block communications between the suction ports and the ejection ports is disposed between the mechanical pump and the electrical pump.
摘要翻译：可以容易地设置电泵的油泵装置。一种机械泵，包括：构造成由发动机驱动的内齿轮; 以及外齿轮，其构造成与所述内齿轮啮合;以及电泵，包括：外齿轮，其被构造成由马达部驱动; 并且构造成与外齿轮啮合的内齿轮在具有吸入口和排出口的泵壳体的泵安装空间中沿轴向彼此相邻地安装。被配置为阻止吸入口和排出口之间的通信的阻挡板设置在机械泵和电动泵之间。

14. 发明授权

US08786056B2 Semiconductor light emitting elements comprising a plating substrate with a projecting tab, or comprising an exposed seed layer 有权
标题翻译：半导体发光元件包括具有突出突片的电镀基板，或包括暴露的种子层
公开(公告)号：US08786056B2
公开(公告)日：2014-07-22
申请号：US13156150
申请日：2011-06-08
申请人： Kentaro Watanabe , Giichi Marutsuki , Yuya Yamakami
发明人： Kentaro Watanabe , Giichi Marutsuki , Yuya Yamakami
IPC分类号： H01L23/544
CPC分类号： H01L33/0075 , H01L33/0025 , H01L33/007 , H01L33/0079 , H01L2933/0033
摘要： A method of forming a semiconductor light emitting element. The method can include forming a seed layer on a semiconductor layer assembly including at least one nitride semiconductor layer. An insulating mask can be formed on the seed layer. The insulating mask can include a plurality of element areas separated by cross spaces. Each element area of the plurality of element areas can be connected to at least one of the other element areas of the plurality of element areas. The seed layer can be plated such that a plating substrate is formed in each of the plurality of element areas.
摘要翻译：一种形成半导体发光元件的方法。该方法可以包括在包括至少一个氮化物半导体层的半导体层组件上形成晶种层。可以在种子层上形成绝缘掩模。绝缘掩模可以包括由交叉空间分开的多个元件区域。多个元件区域中的每个元件区域可以连接到多个元件区域中的至少一个其它元件区域。种子层可以进行电镀，使得在多个元件区域中的每一个中形成镀覆衬底。

15. 发明授权

US08299501B2 Nitride semiconductor device 有权
标题翻译：氮化物半导体器件
公开(公告)号：US08299501B2
公开(公告)日：2012-10-30
申请号：US12155070
申请日：2008-05-29
申请人： Kentaro Watanabe , Shunsuke Minato , Giichi Marutsuki
发明人： Kentaro Watanabe , Shunsuke Minato , Giichi Marutsuki
IPC分类号： H01L21/28
CPC分类号： H01L21/28017 , H01L21/6835 , H01L21/743 , H01L33/0079 , H01L33/32 , H01L33/38 , H01L33/387 , H01L33/40 , H01L2221/6835 , H01L2933/0016
摘要： In the nitride semiconductor device using the silicon substrate, the metal electrode formed on the silicon substrate has both ohmic contact property and adhesion, so that the nitride semiconductor device having excellent electric properties and reliability is obtained. The nitride semiconductor device includes a silicon substrate (2), a nitride semiconductor layer (10) formed on the silicon substrate (2), and metal electrodes (8, 8′) formed in contact with the silicon substrate (2). The metal electrodes (8, 8′) has first metal layers (4, 4′) which are formed in a shape of discrete islands and in contact with the silicon substrate (2), and second metal layers (6, 6′) which are in contact with the silicon substrate (2) exposed among the islands of the first metal layers (4, 4′) and are formed to cover the first metal layers (4, 4′). Further, the second metal layers (6, 6′) are made of a metal capable of forming ohmic contact with silicon, and the first metal layers (4, 4′) are made of an alloy containing a metal and silicon, in which the metal is different than that in the second metal layer (6,6′).
摘要翻译：在使用硅衬底的氮化物半导体器件中，形成在硅衬底上的金属电极具有欧姆接触性和粘合性，从而获得具有优异的电性能和可靠性的氮化物半导体器件。氮化物半导体器件包括硅衬底（2），形成在硅衬底（2）上的氮化物半导体层（10）和与硅衬底（2）接触形成的金属电极（8,8'）。金属电极（8,8'）具有形成离散岛状并与硅衬底（2）接触的第一金属层（4,4'），以及第二金属层（6,6'），其中与在第一金属层（4,4'）的岛之间暴露的硅衬底（2）接触并形成以覆盖第一金属层（4,4'）。此外，第二金属层（6,6'）由能够与硅形成欧姆接触的金属制成，并且第一金属层（4,4'）由含有金属和硅的合金制成，其中金属与第二金属层（6,6'）不同。

16. 发明授权

US08191069B2 Method of monitoring performance of virtual computer and apparatus using the method 有权
标题翻译：使用该方法监测虚拟计算机和设备性能的方法
公开(公告)号：US08191069B2
公开(公告)日：2012-05-29
申请号：US11857820
申请日：2007-09-19
申请人： Kentaro Watanabe , Yoshimasa Masuoka
发明人： Kentaro Watanabe , Yoshimasa Masuoka
IPC分类号： G06F9/455 , G06F9/46
CPC分类号： G06F11/3409 , G06F11/0712 , G06F11/0793 , G06F11/3442 , G06F11/3476 , G06F2201/815 , G06F2201/865
摘要： Provided are a method and an apparatus for monitoring performance of a virtual computer. In a method of controlling a computer system including a computer, the computer executes a virtualization program for causing logically divided resources of the computer to operate as first and second virtual computers, the first virtual computer executes a first OS, and the second virtual computer executes a second OS. In the method, information regarding the resources allocated to the first virtual computer and the second virtual computer by the virtualization program is obtained from the virtualization program, information indicating performance of the first virtual computer is obtained from the first OS, information indicating performance of the second virtual computer is obtained from the second OS, the obtained information and information indicating a time of obtainment of the information are stored in a storage system, and stored information is output.
摘要翻译：提供了一种用于监视虚拟计算机的性能的方法和装置。在控制包括计算机的计算机系统的方法中，计算机执行用于使计算机的逻辑划分的资源作为第一和第二虚拟计算机操作的虚拟化程序，第一虚拟计算机执行第一OS，并且第二虚拟计算机执行第二个操作系统。在该方法中，从虚拟化程序获得关于通过虚拟化程序分配给第一虚拟计算机和第二虚拟计算机的资源的信息，从第一OS获得表示第一虚拟计算机的性能的信息，从第二OS获得第二虚拟计算机，获取的信息和指示获取信息的时间的信息被存储在存储系统中，并且输出存储的信息。

17. 发明申请

US20110303894A1 SEMICONDUCTOR LIGHT EMITTING ELEMENT AND FABRICATING METHOD 有权
标题翻译：半导体发光元件和制造方法
公开(公告)号：US20110303894A1
公开(公告)日：2011-12-15
申请号：US13156150
申请日：2011-06-08
申请人： Kentaro Watanabe , Giichi Marutsuki , Yuya Yamakami
发明人： Kentaro Watanabe , Giichi Marutsuki , Yuya Yamakami
IPC分类号： H01L33/06 , H01L33/08
CPC分类号： H01L33/0075 , H01L33/0025 , H01L33/007 , H01L33/0079 , H01L2933/0033
摘要： A method of forming a semiconductor light emitting element. The method can include forming a seed layer on a semiconductor layer assembly including at least one nitride semiconductor layer. An insulating mask can be formed on the seed layer. The insulating mask can include a plurality of element areas separated by cross spaces. Each element area of the plurality of element areas can be connected to at least one of the other element areas of the plurality of element areas. The seed layer can be plated such that a plating substrate is formed in each of the plurality of element areas.
摘要翻译：一种形成半导体发光元件的方法。该方法可以包括在包括至少一个氮化物半导体层的半导体层组件上形成晶种层。可以在种子层上形成绝缘掩模。绝缘掩模可以包括由交叉空间分开的多个元件区域。多个元件区域中的每个元件区域可以连接到多个元件区域中的至少一个其它元件区域。种子层可以进行电镀，使得在多个元件区域中的每一个中形成镀覆衬底。

18. 发明授权

US08065639B2 Semiconductor integrated circuit designing method 有权
标题翻译：半导体集成电路设计方法
公开(公告)号：US08065639B2
公开(公告)日：2011-11-22
申请号：US12136230
申请日：2008-06-10
申请人： Kentaro Watanabe
发明人： Kentaro Watanabe
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78 , H01L27/0251
摘要： An IC designing method includes planning placement of a first isolated-power supplied region operating between common ground and power bus lines during a normal operation, and second/third isolated-power supplied regions each operating between the common ground bus line and first/second isolated power lines and supplied with potentials different from the common power supply, planning placement of first electrostatic protection circuits connected between the common ground power bus lines and between the common ground bus line and the first/second isolated power lines, and second electrostatic protection circuits connected between the first/second isolated power lines and the common power bus lines, judging presence of a signal transmission between non-adjacent regions among the first to third isolated-power supplied regions, and amending the circuit to insert a buffer circuit powered by the common power bus line in a transmission path when the signal transmission is present.
摘要翻译： IC设计方法包括在正常操作期间规划在公共接地和电源总线之间工作的第一隔离电源供应区域的布置以及在公共地线总线与第一/第二隔离之间工作的第二/第三隔离电源供应区域电源线并提供与公共电源不同的电位，规划连接在公共地电源总线之间以及公共接地总线与第一/第二隔离电源线之间的第一静电保护电路的布置，以及连接的第二静电保护电路在第一/第二隔离电源线和公共电源总线之间，判断在第一至第三隔离电源提供区域之间的非相邻区域之间的信号传输的存在，以及修改电路以插入由公共电源供电的缓冲电路当信号传输存在时，传输路径中的电力总线线路。

19. 发明授权

US07889469B2 Electrostatic discharge protection circuit for protecting semiconductor device 失效
标题翻译：用于保护半导体器件的静电放电保护电路
公开(公告)号：US07889469B2
公开(公告)日：2011-02-15
申请号：US12236045
申请日：2008-09-23
申请人： Kentaro Watanabe
发明人： Kentaro Watanabe
IPC分类号： H02H3/22
CPC分类号： H02H9/046
摘要： A discharge circuit holds the potential difference between a power supply terminal and reference potential terminal at a predetermined value. The gates of a first pMOSFET and first nMOSFET are connected to an input terminal. A second pMOSFET is connected between the first pMOSFET and power supply terminal, and has a gate to which a first signal is supplied. A second nMOSFET is connected between the first nMOSFET and reference potential terminal, and has a gate to which a second signal is supplied. A detection circuit outputs the first signal which turns on the second pMOSFET and the second signal which turns on the second nMOSFET, while the potential difference is held at the predetermined value. The detection circuit outputs the first signal which turns off the second pMOSFET and the second signal which turns off the second nMOSFET, while the potential difference deviates from the predetermined value.
摘要翻译：放电电路将电源端子和参考电位端子之间的电位差保持在预定值。第一pMOSFET和第一nMOSFET的栅极连接到输入端。第二个pMOSFET连接在第一个pMOSFET和电源端子之间，并具有一个提供第一个信号的栅极。第二nMOSFET连接在第一nMOSFET和参考电位端之间，并且具有提供第二信号的栅极。检测电路输出导通第二pMOSFET的第一信号和导通第二nMOSFET的第二信号，同时电位差保持在预定值。检测电路输出关闭第二pMOSFET的第一信号和关闭第二nMOSFET的第二信号，同时电位差偏离预定值。

20. 发明申请

US20100241373A1 ESD PROTECTION VERIFICATION APPARATUS AND METHOD 审中-公开
标题翻译： ESD保护验证装置和方法
公开(公告)号：US20100241373A1
公开(公告)日：2010-09-23
申请号：US12715580
申请日：2010-03-02
申请人： Kentaro Watanabe
发明人： Kentaro Watanabe
IPC分类号： G01R31/02
CPC分类号： G06F17/5081 , G06F2217/14 , H01L27/0255
摘要： An ESD protection verification apparatus of an aspect of the present invention including an element extraction unit which extracts one or more elements connected to a first pad included in design data for a semiconductor integrated circuit, a first and second element information checking/processing unit which checks connection information for the extracted element and which calculates a operating value based on design information for the extracted element, a first and second error detection unit which compares a reference value with the operating value to determine whether the element has a predetermined ESD withstand voltage.
摘要翻译：本发明的ESD保护验证装置，包括提取与半导体集成电路的设计数据中包含的与第一焊盘连接的一个以上的元件的元件提取部，第一和第二元件信息检查/处理部，连接信息，其基于所提取的元素的设计信息计算操作值;第一和第二错误检测单元，其将参考值与操作值进行比较，以确定元件是否具有预定的ESD耐受电压。

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