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11. 发明申请

US20100231306A1 POWER MANAGEMENT ARCHITECTURE AND METHOD OF MODULATING OSCILLATOR FREQUENCY BASED ON VOLTAGE SUPPLY 有权
标题翻译：电源管理架构和基于电压供应调制振荡器频率的方法
公开(公告)号：US20100231306A1
公开(公告)日：2010-09-16
申请号：US12787167
申请日：2010-05-25
申请人： Kenneth J. GOODNOW , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
发明人： Kenneth J. GOODNOW , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： H03L7/00 , G06F17/50
CPC分类号： H03K3/0315
摘要： A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.
摘要翻译：一种基于电压源调制逻辑时钟振荡器频率的方法和系统。该系统包括具有逻辑操作的逻辑单元和用于产生自适应时钟以匹配逻辑运算的装置。该器件被配置为使用电源电压作为独立变量来优化电压变化的器件参数。本发明还涉及电路所在的设计结构。

12. 发明申请

US20090287905A1 PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS 有权
标题翻译：处理器管道结构逻辑状态保持系统和方法
公开(公告)号：US20090287905A1
公开(公告)日：2009-11-19
申请号：US12121292
申请日：2008-05-15
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/3867 , G06F1/32 , G06F1/3287 , G06F11/1407 , G06F11/1441 , Y02D10/171
摘要： A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.
摘要翻译：公开了一种用于保留处理器流水线架构的逻辑状态的解决方案。比较器位于处理器流水线架构的两个阶段之间。存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。提供了与早期输出值相同的参考逻辑。逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态电容器。提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

13. 发明申请

US20100333058A1 METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES 审中-公开
标题翻译：增加可编程逻辑器件制造工艺的方法
公开(公告)号：US20100333058A1
公开(公告)日：2010-12-30
申请号：US12875517
申请日：2010-09-03
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G11C17/14 , G11C29/88 , H03K19/17764 , H03K19/17796
摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAs) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.
摘要翻译：一种提高现场可编程门阵列（FPGA）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

14. 发明授权

US07793251B2 Method for increasing the manufacturing yield of programmable logic devices 失效
标题翻译：提高可编程逻辑器件制造产量的方法
公开(公告)号：US07793251B2
公开(公告)日：2010-09-07
申请号：US11275536
申请日：2006-01-12
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G11C17/14 , G11C29/88 , H03K19/17764 , H03K19/17796
摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.
摘要翻译：一种提高现场可编程门阵列（FPGAS）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

15. 发明授权

US08174329B2 Power management architecture and method of modulating oscillator frequency based on voltage supply 有权
标题翻译：基于电源供电的电源管理架构和调制振荡器频率的方法
公开(公告)号：US08174329B2
公开(公告)日：2012-05-08
申请号：US12787167
申请日：2010-05-25
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
IPC分类号： H03K3/03 , H03L5/02
CPC分类号： H03K3/0315
摘要： A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.
摘要翻译：一种基于电压源调制逻辑时钟振荡器频率的方法和系统。该系统包括具有逻辑操作的逻辑单元和用于产生自适应时钟以匹配逻辑运算的装置。该器件被配置为使用电源电压作为独立变量来优化电压变化的器件参数。本发明还涉及电路所在的设计结构。

16. 发明授权

US07512813B2 Method for system level protection of field programmable logic devices 失效
标题翻译：现场可编程逻辑器件的系统级保护方法
公开(公告)号：US07512813B2
公开(公告)日：2009-03-31
申请号：US10709809
申请日：2004-05-28
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds
IPC分类号： G06F9/00 , G06F15/177 , G06F12/14 , G06F13/16 , G06F13/36 , H04L9/14 , G06F12/16 , H04L9/20 , H04K1/00
CPC分类号： G06F21/76
摘要： A method for protecting a dynamically reconfigurable computing system includes generating an encoding key and passing the encoding key, through a system level bus, to at least one field programmable logic device and to a function library included within the system. The function library contains a plurality of functions for selective programming into the at least one field programmable logic device. A lock is generated so as to prevent external resources with respect to the system from accessing the encoding key during the passing thereof.
摘要翻译：一种用于保护动态可重新配置的计算系统的方法包括生成编码密钥并将编码密钥通过系统级总线传递到至少一个现场可编程逻辑设备和包括在系统内的功能库。功能库包含用于对至少一个现场可编程逻辑器件进行选择性编程的多个功能。产生锁，以防止相对于系统的外部资源在通过期间访问编码密钥。

17. 发明授权

US07373567B2 System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA 有权
标题翻译：使用嵌入式FPGA的冗余逻辑单元在集成电路中提供错误检测和校正能力的系统和方法
公开(公告)号：US07373567B2
公开(公告)日：2008-05-13
申请号：US10709754
申请日：2004-05-26
申请人： John M. Cohn , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
发明人： John M. Cohn , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/318558 , G06F11/261 , H03K19/00392
摘要： A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic function, such that logic EC is provided within the embedded FPGA structure of the IC chip.
摘要翻译：一种使用冗余逻辑单元和嵌入式现场可编程门阵列（FPGA）在IC中提供错误检测和校正能力的系统和方法。该系统和方法提供纠错（EC），以使得能够替换在IC芯片设计中实现的故障逻辑功能，其中在IC芯片中提供至少一个嵌入式FPGA以执行逻辑功能。如果在IC设计中识别到故障逻辑功能，嵌入式FPGA将被编程为正确执行故障逻辑功能。识别故障逻辑功能逻辑输入锥中的所有输入，并将其引导到嵌入式FPGA中，使嵌入式FPGA执行故障逻辑功能的逻辑功能。识别故障逻辑功能的逻辑输出锥中的所有输出，并将FPGA的输出引导到故障逻辑功能的逻辑输出锥，使得在IC的嵌入式FPGA结构内提供逻辑EC 芯片。

18. 发明授权

US07644327B2 System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA 失效
标题翻译：使用嵌入式FPGA的冗余逻辑单元在集成电路中提供错误检测和校正能力的系统和方法
公开(公告)号：US07644327B2
公开(公告)日：2010-01-05
申请号：US12049166
申请日：2008-03-14
申请人： John M. Cohn , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
发明人： John M. Cohn , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/318558 , G06F11/261 , H03K19/00392
摘要： A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic unction, such that logic EC is provided within the embedded FPGA structure of the IC chip.
摘要翻译：一种使用冗余逻辑单元和嵌入式现场可编程门阵列（FPGA）在IC中提供错误检测和校正能力的系统和方法。该系统和方法提供纠错（EC），以使得能够替换在IC芯片设计中实现的故障逻辑功能，其中在IC芯片中提供至少一个嵌入式FPGA以执行逻辑功能。如果在IC设计中识别到故障逻辑功能，嵌入式FPGA将被编程为正确执行故障逻辑功能。识别故障逻辑功能逻辑输入锥中的所有输入，并将其引导到嵌入式FPGA中，使嵌入式FPGA执行故障逻辑功能的逻辑功能。识别有缺陷逻辑功能的逻辑输出锥中的所有输出，并将FPGA的输出引导到故障逻辑逻辑的逻辑输出锥，使得在IC的嵌入式FPGA结构内提供逻辑EC 芯片。

19. 发明申请

US20080163016A1 SYSTEM AND METHOD OF PROVIDING ERROR DETECTION AND CORRECTION CAPABILITY IN AN INTEGRATED CIRCUIT USING REDUNDANT LOGIC CELLS OF AN EMBEDDED FPGA 失效
标题翻译：使用嵌入式FPGA的冗余逻辑单元在集成电路中提供错误检测和校正能力的系统和方法
公开(公告)号：US20080163016A1
公开(公告)日：2008-07-03
申请号：US12049166
申请日：2008-03-14
申请人： John M. Cohn , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
发明人： John M. Cohn , Christopher B. Reynolds , Sebastian T. Ventrone , Paul S. Zuchowski
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318519 , G01R31/318558 , G06F11/261 , H03K19/00392
摘要： A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented within an IC chip design to be replaced, wherein at least one embedded FPGA is provided in the IC chip to perform a logic function. If a defective logic function is identified in the IC design, the embedded FPGA is programmed to correctly perform the defective logic function. All inputs in an input cone of logic of the defective logic function are identified and are directed into the embedded FPGA, such that the embedded FPGA performs the logic function of the defective logic function. All outputs in an output cone of logic of the defective logic function are identified, and the output of the FPGA is directed to the output cone of logic of the defective logic unction, such that logic EC is provided within the embedded FPGA structure of the IC chip.
摘要翻译：一种使用冗余逻辑单元和嵌入式现场可编程门阵列（FPGA）在IC中提供错误检测和校正能力的系统和方法。该系统和方法提供纠错（EC），以使得能够替换在IC芯片设计中实现的故障逻辑功能，其中在IC芯片中提供至少一个嵌入式FPGA以执行逻辑功能。如果在IC设计中识别到故障逻辑功能，嵌入式FPGA将被编程为正确执行故障逻辑功能。识别故障逻辑功能逻辑输入锥中的所有输入，并将其引导到嵌入式FPGA中，使嵌入式FPGA执行故障逻辑功能的逻辑功能。识别有缺陷逻辑功能的逻辑输出锥中的所有输出，并将FPGA的输出引导到故障逻辑逻辑的逻辑输出锥，使得在IC的嵌入式FPGA结构内提供逻辑EC 芯片。

20. 发明授权

US07105385B2 FPGA blocks with adjustable porosity pass thru 失效
标题翻译：具有可调节孔隙度的FPGA块通过
公开(公告)号：US07105385B2
公开(公告)日：2006-09-12
申请号：US10731296
申请日：2003-12-09
申请人： Christopher B. Reynolds , Sebastian T. Ventrone , Angela Weil
发明人： Christopher B. Reynolds , Sebastian T. Ventrone , Angela Weil
IPC分类号： H01L21/82 , H01L21/3205 , H01L21/44 , G06F9/45
CPC分类号： G06F17/5068 , H01L27/11803
摘要： A field programmable gate array is described for use in a semiconductor chip such as a VLSI chip. The array is provided with variable wire-through porosity to allow for optimum chip-level routing through the array. This is achieved by dividing the array into blocks which can be individually assessed for required porosity. Then blocks that have been prefabricated with differing porosities are placed in the macro to optimize local chip level routing. The routing of wires is determined by developing a chip floor plan to include early timing allocation and a proposed placement of the array. The floor plan is then overlaid with critical logical wiring nets. From this, an initial selection of blocks is made based on proposed wiring density, and the macro is assembled with the blocks strategically placed therein. The procedure is likewise applicable to other types of densely obstructed cores embedded with a chip.
摘要翻译：描述了用于诸如VLSI芯片的半导体芯片中的现场可编程门阵列。该阵列具有可变的线穿孔孔，以允许通过阵列的最佳芯片级布线。这是通过将阵列划分成可以单独评估所需孔隙度的块来实现的。然后将具有不同孔隙度的预制块放置在宏中以优化本地芯片级布线。通过开发芯片平面图来确定导线的布线，以包括早期的时序分配和阵列的建议放置。然后将平面图重叠在关键的逻辑布线网上。由此，基于所提出的布线密度进行块的初始选择，并且宏与被策略地放置在其中的块组装。该程序同样适用于嵌入芯片的其他类型的密集阻塞的芯。

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