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11. 发明申请

US20050236181A1 Novel ECP method for preventing the formation of voids and contamination in vias 审中-公开
标题翻译：用于防止通孔中形成空隙和污染的新型ECP方法
公开(公告)号：US20050236181A1
公开(公告)日：2005-10-27
申请号：US10917543
申请日：2004-08-12
申请人： Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen , Ching-Hwan Su , Yu-Ku Lin , Ying-Lang Wang , De-Dui Liao , Meng-Chao Tzeng
发明人： Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen , Ching-Hwan Su , Yu-Ku Lin , Ying-Lang Wang , De-Dui Liao , Meng-Chao Tzeng
IPC分类号： H01L21/768 , H01L23/522 , H05K1/03 , H05K1/09 , H05K1/11
CPC分类号： H01L21/76816 , H01L21/76807 , H01L23/5226 , H01L2924/0002 , Y10T29/49165 , H01L2924/00
摘要： A method for preventing the formation of voids and contaminants in vias during the fabrication of a metal interconnect structure such as a dual damascene structure is disclosed. The method includes providing a substrate; providing a dielectric layer having trench openings and via openings on the substrate, wherein the ratio of the sum of the areas of the trench openings to the sum of the areas of the via openings is between 1 and 300; wherein the via opening bottom has a width of less than about 25 μm; and electroplating a metal in the trench openings and via openings. An interconnect structure having at least one void-free via is further disclosed.
摘要翻译：公开了一种用于在金属互连结构例如双镶嵌结构的制造期间防止在通孔中形成空隙和污染物的方法。该方法包括提供基板; 在衬底上提供具有沟槽开口和通孔开口的电介质层，其中沟槽开口的面积之和与通路孔的面积之和的比值在1和300之间; 其中所述通孔开口底部具有小于约25μm的宽度; 以及在沟槽开口和通孔中电镀金属。还公开了具有至少一个无空隙通孔的互连结构。

12. 发明授权

US06769959B2 Method and system for slurry usage reduction in chemical mechanical polishing 失效
标题翻译：化学机械抛光中浆料用量减少的方法和系统
公开(公告)号：US06769959B2
公开(公告)日：2004-08-03
申请号：US10050314
申请日：2002-01-15
申请人： Kei-Wei Chen , Ting-Chun Wang , Shih-Tzung Chang , Yu-Ku Lin , Ying-Lang Wang , Ming-Wen Chen , Kuo-Hsiu Wei
发明人： Kei-Wei Chen , Ting-Chun Wang , Shih-Tzung Chang , Yu-Ku Lin , Ying-Lang Wang , Ming-Wen Chen , Kuo-Hsiu Wei
IPC分类号： B24B100
CPC分类号： B24B37/04 , B24B57/02
摘要： A method and system is disclosed for reducing slurry usage in a chemical mechanical polishing operation utilizing at least one polishing pad thereof. Slurry can be intermittently supplied to a chemical mechanical polishing device. The slurry is generally flushed so that a portion of said slurry is trapped in a plurality of pores of at least one polishing pad associated with said chemical mechanical polishing device, wherein only a minimum amount of said slurry necessary is utilized to perform said chemical mechanical polishing operation, thereby reducing slurry usage and maintaining a consistent level of slurry removal rate performance and a decrease in particle defects thereof. The present invention thus discloses a method and system for intermittently delivering slurry to a chemical mechanical polishing device in a manner that significantly conserves slurry usage.
摘要翻译：公开了一种利用其至少一个抛光垫在化学机械抛光操作中减少浆料使用的方法和系统。浆料可以间歇地供应到化学机械抛光装置。通常将浆料冲洗，使得所述浆料的一部分被捕获在与所述化学机械抛光装置相关联的至少一个抛光垫的多个孔中，其中仅使用最少量的所需浆料来进行所述化学机械抛光操作，从而减少浆料的使用并保持一致的浆料去除速率性能水平和其颗粒缺陷的减少。因此，本发明公开了一种用于以显着节省浆料使用的方式间歇地将浆料输送到化学机械抛光装置的方法和系统。

13. 发明申请

US20070252277A1 SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070252277A1
公开(公告)日：2007-11-01
申请号：US11380666
申请日：2006-04-28
申请人： Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Jung-Chih Tsao , Kei-Wei Chen , Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/76844 , H01L21/76865 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device. The semiconductor device includes a substrate, a dielectric layer formed thereon, an opening formed in the dielectric layer, a first barrier layer overlying the sidewall of the opening, a second barrier layer overlying the first barrier layer and the bottom of the opening, and a conductive layer filled into the opening. The invention also provides a method of fabricating the semiconductor device.
摘要翻译：半导体器件。所述半导体器件包括：衬底，形成在其上的电介质层，形成在所述电介质层中的开口;覆盖所述开口侧壁的第一阻挡层，覆盖所述第一阻挡层和所述开口底部的第二势垒层;以及导电层填充入开口。本发明还提供一种制造半导体器件的方法。

14. 发明授权

US06626741B2 Method for improving thickness uniformity on a semiconductor wafer during chemical mechanical polishing 有权
公开(公告)号：US06626741B2
公开(公告)日：2003-09-30
申请号：US09910633
申请日：2001-07-20
申请人： Ting-Chun Wang , Kei-Wei Chen , Shih-Tzung Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Ting-Chun Wang , Kei-Wei Chen , Shih-Tzung Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： B24B100
CPC分类号： B24B57/02 , B24B37/042
摘要： A method for improving thickness uniformity on a semiconductor wafer during a chemical mechanical polishing process capable of eliminating a wafer edge collapsing defect is described. In the method, slurry solution is removed from a peripheral edge portion of less than 10 mm wide on the surface of the polishing pad such that a concentration of the slurry can be effectively reduced in the peripheral region. The reduced slurry solution leads to a reduction in the removal rate on the wafer surface. The removal of slurry from the peripheral region can further be achieved by a mechanical means. A suitable width of the peripheral region of the polishing pad to be sprayed by an edge sprayer is less than 10 mm, and preferably between about 3 mm and about 5 mm. A suitable solvent to be sprayed is deionized water.

15. 发明授权

US08099861B2 Current-leveling electroplating/electropolishing electrode 有权
标题翻译：电流调平电镀/电解抛光电极
公开(公告)号：US08099861B2
公开(公告)日：2012-01-24
申请号：US12854214
申请日：2010-08-11
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen
IPC分类号： B23P19/02 , B23P19/04 , B23P19/10 , B23P19/12 , C25D17/12 , C25D17/14 , C25D3/38
CPC分类号： H01L21/2885 , C25D17/001 , C25D17/12 , Y10T29/49208 , Y10T29/53204
摘要： A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.
摘要翻译：公开了一种用于改善电化学电镀中的电镀和电化学抛光均匀性的电流调节电极或对基底上的金属的电解抛光。电流调平电极包括基极和由基极承载的至少一个子电极。所述至少一个子电极的宽度小于所述基极的宽度，以赋予所述电流调平电极大致锥形，阶梯形或凸形的构造。

16. 发明申请

US20100314256A1 CURRENT-LEVELING ELECTROPLATING/ELECTROPOLISHING ELECTRODE 有权
标题翻译：电流电镀/电镀电极
公开(公告)号：US20100314256A1
公开(公告)日：2010-12-16
申请号：US12854214
申请日：2010-08-11
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen
IPC分类号： C25D5/00 , H01R43/00 , C25F3/16 , C25F3/22
CPC分类号： H01L21/2885 , C25D17/001 , C25D17/12 , Y10T29/49208 , Y10T29/53204
摘要： A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.
摘要翻译：公开了一种用于改善电化学电镀中的电镀和电化学抛光均匀性的电流调节电极或对基底上的金属的电解抛光。电流调平电极包括基极和由基极承载的至少一个子电极。所述至少一个子电极的宽度小于所述基极的宽度，以赋予所述电流调平电极大致锥形，阶梯形或凸形的构造。

17. 发明授权

US07803257B2 Current-leveling electroplating/electropolishing electrode 有权
标题翻译：电流调平电镀/电解抛光电极
公开(公告)号：US07803257B2
公开(公告)日：2010-09-28
申请号：US10971836
申请日：2004-10-22
申请人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen
发明人： Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Shih-Ho Lin , Chun-Chang Chen
IPC分类号： C25D17/14 , C25D17/12
CPC分类号： H01L21/2885 , C25D17/001 , C25D17/12 , Y10T29/49208 , Y10T29/53204
摘要： A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.
摘要翻译：公开了一种用于改善电化学电镀中的电镀和电化学抛光均匀性的电流调节电极或对基底上的金属的电解抛光。电流调平电极包括基极和由基极承载的至少一个子电极。所述至少一个子电极的宽度小于所述基极的宽度，以赋予所述电流调平电极大致锥形，阶梯形或凸形的构造。

18. 发明申请

US20090127097A1 Forming Seed Layer in Nano-Trench Structure Using Net Deposition and Net Etch 审中-公开
标题翻译：使用净沉积和净蚀刻在纳米沟槽结构中形成种子层
公开(公告)号：US20090127097A1
公开(公告)日：2009-05-21
申请号：US11941435
申请日：2007-11-16
申请人： Kei-Wei Chen , Shih-Ho Lin , Yu-Sheng Wang , Szu-An Wu , Ying-Lang Wang
发明人： Kei-Wei Chen , Shih-Ho Lin , Yu-Sheng Wang , Szu-An Wu , Ying-Lang Wang
IPC分类号： C23C14/00
CPC分类号： C23C14/345 , C23C14/046 , H01L21/76862 , H01L21/76873
摘要： A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a net deposition step to form a seed layer having a portion in the opening, wherein the net deposition step comprises a first deposition and a first etching; performing a net etch step to the seed layer, wherein the net etch step comprises a first etching and a first deposition, wherein a portion of the seed layer remains after the net etch step; and growing a conductive material on the seed layer to fill a remaining portion of the opening.
摘要翻译：形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行净沉积步骤以形成具有在开口中的一部分的种子层，其中所述净沉积步骤包括第一沉积和第一蚀刻; 对所述种子层进行净蚀刻步骤，其中所述净蚀刻步骤包括第一蚀刻和第一沉积，其中所述种子层的一部分在所述净蚀刻步骤之后保留; 以及在种子层上生长导电材料以填充开口的剩余部分。

19. 发明授权

US08470390B2 Oxidation-free copper metallization process using in-situ baking 有权
标题翻译：无氧化铜金属化工艺采用原位烘烤
公开(公告)号：US08470390B2
公开(公告)日：2013-06-25
申请号：US11972785
申请日：2008-01-11
申请人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
IPC分类号： B05D5/12 , C23C14/00
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76828 , H01L21/76843
摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer.
摘要翻译：形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。金属特征的至少一部分通过开口露出。相应地，在金属特征的暴露部分上形成氧化物层。该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层。

20. 发明申请

US20090181164A1 Oxidation-Free Copper Metallization Process Using In-situ Baking 有权
标题翻译：使用原位烘烤的无氧铜金属化工艺
公开(公告)号：US20090181164A1
公开(公告)日：2009-07-16
申请号：US11972785
申请日：2008-01-11
申请人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
IPC分类号： H05K3/46
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76828 , H01L21/76843
摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer
摘要翻译：形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。金属特征的至少一部分通过开口露出。相应地，在金属特征的暴露部分上形成氧化物层。该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层

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