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11. 发明授权

US08013360B2 Semiconductor device having a junction of P type pillar region and N type pillar region 有权
标题翻译：具有P型支柱区域和N型支柱区域的结的半导体器件
公开(公告)号：US08013360B2
公开(公告)日：2011-09-06
申请号：US12764763
申请日：2010-04-21
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/66
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/7395 , H01L29/7397 , H01L29/7722 , H01L29/7806 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。高电阻半导体层的掺杂浓度低于第一半导体柱区域。边界区域设置在设备中心区域和边缘终端部分之间。边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

12. 发明申请

US20110065667A1 PHENYLPYRAZOLE DERIVATIVES 有权
公开(公告)号：US20110065667A1
公开(公告)日：2011-03-17
申请号：US12951964
申请日：2010-11-22
申请人： Toshio NAKAMURA , Makoto Tatsuzuki , Dai Nozawa , Tomoko Tamita , Seiji Masuda , Hiroshi Ohta , Shuhei Kashiwa , Aya Fujino , Shigeyuki Chaki , Toshiharu Shimazaki
发明人： Toshio NAKAMURA , Makoto Tatsuzuki , Dai Nozawa , Tomoko Tamita , Seiji Masuda , Hiroshi Ohta , Shuhei Kashiwa , Aya Fujino , Shigeyuki Chaki , Toshiharu Shimazaki
IPC分类号： A61K31/695 , C07D231/10 , C07D413/12 , C07D281/06 , C07F7/10 , A61K31/415 , A61K31/5377 , A61K31/553 , A61P25/28 , A61P25/18 , A61P3/10 , A61P25/24 , A61P25/08 , A61P25/00
CPC分类号： C07D231/14 , C07D231/40 , C07D401/04 , C07D401/14 , C07D403/04 , C07D403/06 , C07D403/12 , C07D403/14 , C07D413/04 , C07D413/14
摘要： The present invention provides a prophylactic or therapeutic agent for dementia, Alzheimer's disease, attention-deficit hyperactivity disorder, schizophrenia, eating disorders, obesity, diabetes, hyperlipidemia, sleep disorders, narcolepsy, sleep apnea syndrome, circadian rhythm disorder, depression, allergic rhinitis or other diseases.A phenylpyrazole derivative represented by formula (1) or a pharmaceutically acceptable salt thereof: {wherein R1 and R2, which may be the same or different, each represent C1-C6 alkyl or C3-C8 cycloalkyl, or R1 and R2 are attached to each other together with their adjacent nitrogen atom to form a 4- to 7-membered saturated heterocyclic ring (wherein said saturated heterocyclic ring may be substituted with halogen or C1-C6 alkyl), n represents an integer of 0 to 2, T represents a hydrogen atom, halogen or C1-C6 alkyl, and R represents formula (I): or the like}.

13. 发明授权

US07802868B2 Nozzle plate, method of manufacturing nozzle plate, liquid ejection head and image forming apparatus 失效
标题翻译：喷嘴板，喷嘴板的制造方法，喷液头和成像装置
公开(公告)号：US07802868B2
公开(公告)日：2010-09-28
申请号：US12027896
申请日：2008-02-07
申请人： Hiroshi Ohta
发明人： Hiroshi Ohta
IPC分类号： B41J2/045
CPC分类号： B41J2/1433 , B41J2/1606 , B41J2/162 , B41J2/1642 , Y10T29/49401
摘要： The nozzle plate has: a first metal layer in which a hole section corresponding to a nozzle hole is formed; a liquid-repellent layer formed on a front surface of the first metal layer, an inner surface of the hole section in the first metal layer, and an opening perimeter region of the hole section on a rear surface of the first metal layer; and a second metal layer formed on a rear surface side of the first metal layer, wherein the liquid-repellent layer on the rear surface of the first metal layer is sandwiched between the first metal layer and the second metal layer.
摘要翻译：喷嘴板具有：形成与喷嘴孔对应的孔部的第一金属层; 形成在第一金属层的前表面上的防液层，第一金属层中的孔部的内表面和第一金属层的后表面上的孔部的开口周边区域; 以及形成在所述第一金属层的背面侧的第二金属层，其中，所述第一金属层的背面上的所述排斥层夹在所述第一金属层和所述第二金属层之间。

14. 发明申请

US20100233004A1 Air Compressor of Water Injection Type 有权
标题翻译：注水型空气压缩机
公开(公告)号：US20100233004A1
公开(公告)日：2010-09-16
申请号：US12709275
申请日：2010-02-19
申请人： Takehiro MATSUZAKA , Hiroshi Ohta
发明人： Takehiro MATSUZAKA , Hiroshi Ohta
IPC分类号： F04C29/04
CPC分类号： F04C29/0014 , F04B39/06 , F04B39/062 , F04C18/16 , F04C2210/128 , F04C2280/04
摘要： In a water injection air compressor including a compressor main body for compressing air, a water-feed line for feeding water to an actuation chamber in the compressor main body, an air release valve for releasing the compressed air from the compressor main body, and a control panel for executing an on-load operation mode in which water is fed into the actuation chamber and an air release valve is closed and a no-load operation mode in which the water is fed into the actuation chamber and the air release valve is opened, wherein the control panel further executes a dry operation mode in which the water is prevented from being fed into the actuation chamber and with the air release valve is opened.
摘要翻译：在包括用于压缩空气的压缩机主体的水注射空气压缩机中，将水供给到压缩机主体中的致动室的供水管线，用于从压缩机主体释放压缩空气的排气阀，以及控制面板，用于执行其中水被供给到致动室中的空载操作模式和空气释放阀关闭，以及空气操作模式，其中水被供给到致动室和排气阀打开其特征在于，所述控制面板进一步执行干式运转模式，在所述干式运转模式中，防止水进入所述致动室，并且所述排气阀打开。

15. 发明申请

US20100200936A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100200936A1
公开(公告)日：2010-08-12
申请号：US12764763
申请日：2010-04-21
申请人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Wataru SAITO , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/78
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/7395 , H01L29/7397 , H01L29/7722 , H01L29/7806 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。高电阻半导体层的掺杂浓度低于第一半导体柱区域。边界区域设置在设备中心区域和边缘终端部分之间。边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

16. 发明授权

US07759732B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US07759732B2
公开(公告)日：2010-07-20
申请号：US11680912
申请日：2007-03-01
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
IPC分类号： H01L27/088 , H01L23/62
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.
摘要翻译：功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和形成在第一半导体层上的第二导电类型的第三半导体层，并且沿着平行于第一半导体层的表面的至少一个方向交替布置; 第一主电极; 选择性地形成在第二半导体层的表面和第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地形成在第四半导体层的表面中的第一导电类型的第五半导体层; 第二主电极; 和控制电极。第二和第三半导体层中的至少一个具有沿着一个方向的掺杂剂浓度分布，掺杂剂浓度分布在其两端以外的位置处具有局部最小值。

17. 发明授权

US07755138B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07755138B2
公开(公告)日：2010-07-13
申请号：US12537219
申请日：2009-08-06
申请人： Wataru Saito , Syotaro Ono , Nana Hatano , Hiroshi Ohta , Miho Watanabe
发明人： Wataru Saito , Syotaro Ono , Nana Hatano , Hiroshi Ohta , Miho Watanabe
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/7806
摘要： A semiconductor device of the invention includes: a super junction structure of an n-type pillar layer and a p-type pillar layer; a base layer provided on the p-type pillar layer; a source layer selectively provided on a surface of the base layer; a gate insulating film provided on a portion being in contact with the base layer, a portion being in contact with the source layer and a portion being in contact with the n-type pillar layer on a portion of a junction between the n-type pillar layer and the p-type pillar layer; a control electrode provided opposed to the base layer, the source layer and the n-type pillar layer through the gate insulating film; and a source electrode electrically connected to the base layer, the source layer and the n-type layer. The source electrode is contact with the surface of the n-type pillar layer located between the control electrodes to form a Schottky junction.
摘要翻译：本发明的半导体器件包括：n型柱层和p型柱层的超结结构; 设置在p型支柱层上的基底层; 源层选择性地设置在基层的表面上; 设置在与所述基底层接触的部分上的栅极绝缘膜，与所述源极层接触的部分和在所述n型支柱的接合部的一部分上与所述n型支柱层接触的部分层和p型支柱层; 控制电极，其通过所述栅极绝缘膜与所述基极层，所述源极层和所述n型支柱层相对设置; 以及与基极层，源极层和n型层电连接的源电极。源电极与位于控制电极之间的n型支柱层的表面接触以形成肖特基结。

18. 发明申请

US20090306408A1 2-Amino-Bicyclo (3.1.0) Hexane-2,6-Dicarboxylic Ester Derivative 失效
标题翻译： 2-氨基 - 双环（3.1.0）己烷-2,6-二羧酸酯衍生物
公开(公告)号：US20090306408A1
公开(公告)日：2009-12-10
申请号：US12511482
申请日：2009-07-29
申请人： Akito YASUHARA , Kazunari Sakagami , Hiroshi Ohta , Atsuro Nakazato
发明人： Akito YASUHARA , Kazunari Sakagami , Hiroshi Ohta , Atsuro Nakazato
IPC分类号： C07D317/18 , C07C69/753 , C07D305/12
CPC分类号： C07C229/50 , C07D307/88
摘要： A drug effective for the treatment and prevention of psychiatric disorders such as schizophrenia, anxiety and related ailments thereof, depression, bipolar disorder and epilepsy. The drug antagonizes the action of group II metabotropic glutamate receptors and shows high activity in oral administrationA 2-amino-bicyclo[3.1.0]hexane-2,6-dicarboxylic ester derivative represented by formula [I] [wherein R1 and R2 are identical or different, and each represents a hydrogen atom, a C1-10alkyl group or the like; X represents a hydrogen atom or a fluorine atom; Y represents —OCHR3R4 or the like (wherein R3 and R4 are identical or different, and each represents a hydrogen atom, a C1-10alkyl group or the like; and n represents integer 1 or 2)], a pharmaceutically acceptable salt thereof or a hydrate thereof.
摘要翻译：一种有效治疗和预防精神疾病如精神分裂症，焦虑及其相关疾病，抑郁症，双相情感障碍和癫痫的药物。该药物拮抗II型代谢型谷氨酸受体的作用，并且在口服给药中表现出高活性。由式[I]表示的2-氨基 - 双环[3.1.0]己烷-2,6-二羧酸酯衍生物[其中R1和R2为相同或不同，并且各自表示氢原子，C 1-10烷基等; X表示氢原子或氟原子; Y表示-OCHR 3 R 4等（其中R 3和R 4相同或不同，并且各自表示氢原子，C 1-10烷基等; n表示1或2的整数）]，其药学上可接受的盐或水合物。

19. 发明授权

US07605426B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US07605426B2
公开(公告)日：2009-10-20
申请号：US11933869
申请日：2007-11-01
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： A power semiconductor device includes: a semiconductor substrate; a gate insulating film; a control electrode insulated from the semiconductor substrate by the gate insulating film; a first main electrode provided on a lower surface side of the semiconductor substrate; and a second main electrode provided on an upper surface side of the semiconductor substrate. The semiconductor substrate includes: a first first-conductivity-type semiconductor layer with its lower surface connected to the first main electrode; a second first-conductivity-type semiconductor layer and a third second-conductivity-type semiconductor layer formed on the first first-conductivity-type semiconductor layer and alternately arranged parallel to the upper surface of the semiconductor substrate; a trench formed in a directly overlying region of the third second-conductivity-type semiconductor layer, with part of the second main electrode buried in the trench; a fourth second-conductivity-type semiconductor layer selectively formed in a surface of the second first-conductivity-type semiconductor layer and connected to the second main electrode; a fifth first-conductivity-type semiconductor layer selectively formed in a surface of the fourth second-conductivity-type semiconductor layer and connected to the second main electrode; and a sixth second-conductivity-type semiconductor layer formed at a bottom of the trench and connected to the second main electrode. Impurity concentration in the sixth second-conductivity-type semiconductor layer is higher than impurity concentration in the fourth second-conductivity-type semiconductor layer, and lower surface of the sixth second-conductivity-type semiconductor layer is located below lower surface of the fourth second-conductivity-type semiconductor layer.
摘要翻译：功率半导体器件包括：半导体衬底; 栅极绝缘膜; 通过栅极绝缘膜与半导体衬底绝缘的控制电极; 设置在所述半导体基板的下表面侧的第一主电极; 以及设置在半导体衬底的上表面侧的第二主电极。半导体衬底包括：第一第一导电型半导体层，其下表面连接到第一主电极; 形成在第一第一导电型半导体层上的第二第一导电型半导体层和第三第二导电型半导体层，并且交替地平行于半导体基板的上表面布置; 形成在所述第三第二导电型半导体层的直接覆盖区域中的沟槽，其中所述第二主电极的一部分埋在所述沟槽中; 选择性地形成在所述第二第一导电型半导体层的表面并连接到所述第二主电极的第四第二导电型半导体层; 第五第一导电型半导体层，选择性地形成在所述第四第二导电型半导体层的表面上，并连接到所述第二主电极; 以及形成在所述沟槽的底部并连接到所述第二主电极的第六第二导电型半导体层。第六第二导电型半导体层中的杂质浓度高于第四第二导电型半导体层中的杂质浓度，第六第二导电型半导体层的下表面位于第四第二导电型半导体层的下表面下方导电型半导体层。

20. 发明申请

US20090101974A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090101974A1
公开(公告)日：2009-04-23
申请号：US12252872
申请日：2008-10-16
申请人： Wataru SAITO , Syotaro Ono , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Nana Hatano
发明人： Wataru SAITO , Syotaro Ono , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Nana Hatano
IPC分类号： H01L29/78
CPC分类号： H01L29/0634 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/7811
摘要： A semiconductor device includes an n+ type semiconductor substrate 1 and a super junction region that has, on the top of the substrate 1, an n and p type pillar regions 2 and 3 provided alternately. The device also includes, in the top surface of the super junction region, a p type base region 4 and an n type source layer 5. The device also includes a gate electrode 7 on the region 4 and layer 5 via a gate-insulating film 6, a drain electrode 9 on the bottom of the substrate 1, and a source electrode 8 on the top of the substrate 1. In the top surface of the super junction region in the terminal region, a RESURF region 10 is formed. The RESURF region has a comb-like planar shape with repeatedly-formed teeth having tips facing the end portion of the terminal region.
摘要翻译：半导体器件包括n +型半导体衬底1和超结区，其在衬底1的顶部上交替设置n和p型柱状区域2,3。该器件还在超结区域的顶表面中包括ap型基极区域4和n型源极层5.该器件还包括位于区域4上的栅电极7和通过栅极绝缘膜6的层5 ，基板1底部的漏电极9以及基板1顶部的源极8.在端子区域的超结区域的上表面形成有RESURF区域10。 RESURF区域具有梳状平面形状，具有重复形成的齿，其尖端面向终端区域的端部。

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