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11. 发明授权

US06999360B2 Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device 失效
标题翻译：移位冗余电路，控制移位冗余电路的方法以及半导体存储器件
公开(公告)号：US06999360B2
公开(公告)日：2006-02-14
申请号：US11041287
申请日：2005-01-25
申请人： Kazufumi Komura
发明人： Kazufumi Komura
IPC分类号： G11C7/00
CPC分类号： G11C29/848
摘要： A shift redundancy circuit for enabling switching operation of memory blocks to be executed at a high speed and for reducing current consumption relating to the switching operation. A shift control circuit includes a first shift control circuit for generating a first shift signal corresponding to a first deficiency address of a memory block and a second shift control circuit for generating a second shift signal corresponding to a second deficiency address of a memory block. When the memory blocks are switched, a shift signal controlling the switching of selection line switches are selected from the first shift signal whose state is determined in advance, the second shift signal whose state is determined in advance, and a low potential power supply.
摘要翻译：一种用于使得能够高速执行的存储器块的切换操作和用于减少与开关操作相关的电流消耗的移位冗余电路。移位控制电路包括：第一移位控制电路，用于产生对应于存储块的第一不足地址的第一移位信号;以及第二移位控制电路，用于产生对应于存储块的第二不足地址的第二移位信号。当切换存储器块时，从预先确定其状态的第一移位信号，其状态被预先确定的第二移位信号和低电位电源中选择控制选择线开关切换的移位信号。

12. 发明申请

US20100254208A1 SEMICONDUCTOR MEMORY DEVICE, REFRESH CONTROL METHOD THEREOF, AND TEST METHOD THEREOF 有权
标题翻译：半导体存储器件，其刷新控制方法及其测试方法
公开(公告)号：US20100254208A1
公开(公告)日：2010-10-07
申请号：US12818956
申请日：2010-06-18
申请人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
发明人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
IPC分类号： G11C7/00
CPC分类号： G11C29/50016 , G11C8/18 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/028 , G11C29/50 , G11C29/783 , G11C2207/2227 , G11C2211/4061 , G11C2211/4067
摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.
摘要翻译：本发明提供一种由于适当的刷新稀疏功能而在待机状态下减少电流消耗的半导体存储器件及其刷新控制方法。当刷新操作和外部访问操作彼此独立地执行时添加刷新稀疏功能时，刷新地址计数器输出刷新地址Add（C）并将预定的高位比特输入到刷新 - 作为高阶刷新地址的输出控制Add（C）（m），其中进行关于刷新操作的判断。与判断结果相对应的刷新允许信号RFEN被输入到字驱动器以激活和控制字驱动器。刷新稀疏控制电路的判断处理可嵌入行系统的访问时间。

13. 发明授权

US07764559B2 Semiconductor memory device, refresh control method thereof, and test method thereof 失效
标题翻译：半导体存储器件，其刷新控制方法及其测试方法
公开(公告)号：US07764559B2
公开(公告)日：2010-07-27
申请号：US11715452
申请日：2007-03-08
申请人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
发明人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
IPC分类号： G11C7/00
CPC分类号： G11C29/50016 , G11C8/18 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/028 , G11C29/50 , G11C29/783 , G11C2207/2227 , G11C2211/4061 , G11C2211/4067
摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.
摘要翻译：本发明提供一种由于适当的刷新稀疏功能而在待机状态下减少电流消耗的半导体存储器件及其刷新控制方法。当刷新操作和外部访问操作彼此独立地执行时添加刷新稀疏功能时，刷新地址计数器输出刷新地址Add（C）并将预定的高位比特输入到刷新 - 作为高阶刷新地址的输出控制Add（C）（m），其中进行关于刷新操作的判断。与判断结果相对应的刷新允许信号RFEN被输入到字驱动器以激活和控制字驱动器。刷新稀疏控制电路的判断处理可嵌入行系统的访问时间。

14. 发明授权

US07495990B2 Semiconductor memory device and method of controlling the semiconductor memory device 失效
标题翻译：半导体存储器件和控制半导体存储器件的方法
公开(公告)号：US07495990B2
公开(公告)日：2009-02-24
申请号：US11806721
申请日：2007-06-04
申请人： Kazufumi Komura , Yoshiharu Kato , Satoru Kawamoto
发明人： Kazufumi Komura , Yoshiharu Kato , Satoru Kawamoto
IPC分类号： G11C8/00
CPC分类号： G11C11/4094 , G11C11/4076 , G11C2207/005
摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.
摘要翻译：本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化相等的时间，从而能够防止读出放大器内的短路。

15. 发明申请

US20070187740A1 Capacitance cell, semiconductor device, and capacitance element arranging method 有权
标题翻译：电容电池，半导体器件和电容元件排列方法
公开(公告)号：US20070187740A1
公开(公告)日：2007-08-16
申请号：US11482012
申请日：2006-07-07
申请人： Kazufumi Komura
发明人： Kazufumi Komura
IPC分类号： H01L29/94
CPC分类号： H01L23/5223 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A capacitance cell 21 is wired while using adjacent wiring layers Ma and Mb as a pair of electrode layers T1 and T2 orthogonally to opposed lateral end faces out of lateral end faces X1, X2, Y1, and Y2 that section the cell in a plane direction. Contact surfaces of the electrode surfaces T1 and T2 with the lateral end faces are second connection terminals T12 and T22. For longitudinal pathways, first and second via contact layers V1 and V2are connected. The first via contact layer V1 interconnects the wiring layers Ma and Mb. The second via contact layer V2 is connected to a wiring layer located outside beyond an upper or lower end face Z2, Z1. The second via contact layer V2 is connected to a first connection terminal T11, T21 located on the upper or lower end faces Z2, Z1. The capacitance cells 21 are linked via the first and second connection terminals so that a capacitance element having a free shape is formed. A capacitance cell, a semiconductor device, and a capacitance element arranging method that allow to arrange capacitance elements each using wiring layers sandwiching an interlayer insulating film with less of a leak current as electrode layers according to the shapes of unused areas.
摘要翻译：在使用相邻布线层Ma和Mb作为与侧面X 1，X 2，Y 1和Y 2之间的相对的侧端面正交的一对电极层T 1和T 2之后，电容单元21被布线，该截面电池在平面方向。具有侧端面的电极表面T 1和T 2的接触表面是第二连接端子T12和T22。对于纵向路径，连接第一和第二通孔接触层V 1和V 2。第一通孔接触层V 1将布线层Ma和Mb互连。第二通孔接触层V 2连接到位于外侧或上端面Z 2，Z 1之外的布线层。第二通孔接触层V 2连接到位于上端面或下端面Z 2，Z 1上的第一连接端子T11，T21。电容单元21通过第一和第二连接端子连接，从而形成具有自由形状的电容元件。电容单元，半导体器件和电容元件配置方法，其能够根据未使用区域的形状，使用夹着具有较小漏电流的层间绝缘膜的布线层来布置电容元件作为电极层。

16. 发明授权

US07206246B2 Semiconductor memory device, refresh control method thereof, and test method thereof 有权
公开(公告)号：US07206246B2
公开(公告)日：2007-04-17
申请号：US11249454
申请日：2005-10-14
申请人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
发明人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
IPC分类号： G11C7/00
CPC分类号： G11C29/50016 , G11C8/18 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/028 , G11C29/50 , G11C29/783 , G11C2207/2227 , G11C2211/4061 , G11C2211/4067
摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

17. 发明授权

US07301833B2 Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device 有权
标题翻译：移位冗余电路，控制移位冗余电路的方法以及半导体存储器件
公开(公告)号：US07301833B2
公开(公告)日：2007-11-27
申请号：US11282723
申请日：2005-11-21
申请人： Kazufumi Komura
发明人： Kazufumi Komura
IPC分类号： G11C29/00
CPC分类号： G11C29/848
摘要： A shift redundancy circuit for enabling switching operation of memory blocks to be executed at a high speed and for reducing current consumption relating to the switching operation. A shift control circuit includes a first shift control circuit for generating a first shift signal corresponding to a first deficiency address of a memory block and a second shift control circuit for generating a second shift signal corresponding to a second deficiency address of a memory block. When the memory blocks are switched, a shift signal controlling the switching of selection line switches are selected from the first shift signal whose state is determined in advance, the second shift signal whose state is determined in advance, and a low potential power supply.
摘要翻译：一种用于使得能够高速执行的存储器块的切换操作和用于减少与开关操作相关的电流消耗的移位冗余电路。移位控制电路包括：第一移位控制电路，用于产生对应于存储块的第一不足地址的第一移位信号;以及第二移位控制电路，用于产生对应于存储块的第二不足地址的第二移位信号。当切换存储器块时，从预先确定其状态的第一移位信号，其状态被预先确定的第二移位信号和低电位电源中选择控制选择线开关切换的移位信号。

18. 发明授权

US07245549B2 Semiconductor memory device and method of controlling the semiconductor memory device 有权
标题翻译：半导体存储器件和控制半导体存储器件的方法
公开(公告)号：US07245549B2
公开(公告)日：2007-07-17
申请号：US11058302
申请日：2005-02-16
申请人： Kazufumi Komura , Yoshiharu Kato , Satoru Kawamoto
发明人： Kazufumi Komura , Yoshiharu Kato , Satoru Kawamoto
IPC分类号： G11C8/00
CPC分类号： G11C11/4094 , G11C11/4076 , G11C2207/005
摘要： A semiconductor memory device is provided that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines.
摘要翻译：提供一种半导体存储装置及其控制方法，其可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。此外，根据感测放大电源线和位线的布线容量分量，通过更高的电压电平来驱动均衡电容分量较高的布线的电路。

19. 发明申请

US20070159906A1 Semiconductor memory device, refresh control method thereof, and test method thereof 失效
标题翻译：半导体存储器件，其刷新控制方法及其测试方法
公开(公告)号：US20070159906A1
公开(公告)日：2007-07-12
申请号：US11715452
申请日：2007-03-08
申请人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
发明人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C29/50016 , G11C8/18 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/028 , G11C29/50 , G11C29/783 , G11C2207/2227 , G11C2211/4061 , G11C2211/4067
摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.
摘要翻译：本发明提供一种由于适当的刷新稀疏功能而在待机状态下减少电流消耗的半导体存储器件及其刷新控制方法。当刷新操作和外部访问操作彼此独立地执行时添加刷新稀疏功能时，刷新地址计数器输出刷新地址Add（C）并将预定的高位比特输入到刷新 - 作为高阶刷新地址的输出控制Add（C）（m），其中进行关于刷新操作的判断。与判断结果相对应的刷新允许信号RFEN被输入到字驱动器以激活和控制字驱动器。刷新稀疏控制电路的判断处理可嵌入行系统的访问时间。

20. 发明申请

US20060028893A1 Semiconductor memory device, refresh control method thereof, and test method thereof 有权
公开(公告)号：US20060028893A1
公开(公告)日：2006-02-09
申请号：US11249454
申请日：2005-10-14
申请人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
发明人： Masami Nakashima , Yoshiharu Kato , Kazufumi Komura
IPC分类号： G11C7/00
CPC分类号： G11C29/50016 , G11C8/18 , G11C11/401 , G11C11/406 , G11C11/40603 , G11C29/028 , G11C29/50 , G11C29/783 , G11C2207/2227 , G11C2211/4061 , G11C2211/4067
摘要： The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

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