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    • 13. 发明授权
    • Hermetically sealed semiconductor power module and large scale module comprising the same
    • 密封的半导体功率模块和包括其的大型模块
    • US06756667B2
    • 2004-06-29
    • US09917876
    • 2001-07-31
    • Michiaki Hiyoshi
    • Michiaki Hiyoshi
    • H01L2315
    • H01L25/072H01L2224/45124H01L2224/48091H01L2224/48095H01L2224/48227H01L2224/48464H01L2224/49111H01L2224/73265H01L2924/1301H01L2924/1305H01L2924/13055H01L2924/13091H01L2924/181H01L2924/3025H01L2924/00014H01L2924/00H01L2924/00012
    • This is a semiconductor power module provided with: a ceramic substrate; a metallic plate bonded to a surface of this substrate; a cylindrical metallic flange which is hermetically bonded to a surface of substrate or the metallic plate; a ceramic housing for hermetically sealing an opening of the metallic flange; and at least one or more semiconductor chips soldered to the metallic plate. The metallic flange is made of metal with a low thermal expansion coefficient. A hermetically sealed container is created by welding the metallic flange, the ceramic substrate and the housing with silver brazing. Moreover, external collector, emitter and gate electrodes are bonded on the housing by using the silver brazing. The collector, emitter and gate conductive pillars are respectively connected to the external collector, emitter and gate electrodes with calking. Thus, this hermetically sealed container is strong in mechanical strength and high in explosion-proof durability and excellent in moisture resistance. And this semiconductor power module has a high TFT reliability and a high TCT reliability. Moreover, a power cycle durability is larger since the emitter pedals are pressure-contacted to the emitter electrode pads disposed on the semiconductor chip via the metallic hemispheres so as to implement a large conductive capacity.
    • 这是一种半导体功率模块,具有:陶瓷基板; 金属板结合到该基板的表面上; 圆柱形的金属法兰,气密地粘合到基片或金属板的表面上; 陶瓷壳体,用于密封金属法兰的开口; 以及焊接到金属板的至少一个或多个半导体芯片。 金属法兰由热膨胀系数低的金属制成。 通过用金属钎焊焊接金属法兰,陶瓷基板和外壳来形成气密密封的容器。 此外,通过使用银钎焊将外部集电极,发射极和栅电极接合在壳体上。 集电极,发射极和栅极导电柱分别与外部集电极,发射极和栅电极连接。 因此,该密闭容器的机械强度强,防爆耐久性高,耐湿性优异。 该半导体功率模块具有较高的TFT可靠性和较高的TCT可靠性。 此外,由于发射踏板通过金属半球与设置在半导体芯片上的发射极电极焊盘压力接触以实现大的导电能力,所以功率循环耐久性更大。
    • 18. 发明授权
    • Multichip press-contact type semiconductor device
    • 多芯片压接式半导体器件
    • US5866944A
    • 1999-02-02
    • US665980
    • 1996-06-19
    • Michiaki HiyoshiTakashi FujiwaraHideo Matsuda
    • Michiaki HiyoshiTakashi FujiwaraHideo Matsuda
    • H01L29/74H01L23/051H01L23/48H01L25/04H01L25/07H01L25/18H01L23/16
    • H01L23/051H01L24/72H01L2924/01004H01L2924/01013H01L2924/01029H01L2924/01033H01L2924/01042H01L2924/01047H01L2924/01082H01L2924/1305H01L2924/13055
    • In the present invention, by virtue of heat buffer plates respectively located on the major surfaces of IGBT chips and FRD chips arranged in a single plane, the total thickness of each chip and a corresponding one of the heat can be set to a substantially predetermined value. A thickness-correcting member having elongated projections corresponding to the chips is provided on those surfaces of the heat buffer plates which is remote from the chips. A heat buffer disk plate is provided on those surfaces of the chips which are opposite to the major surfaces thereof. The thickness-correcting member, the heat buffer plates and the IGBT and FRD chips are held and simultaneously pressed between an emitter press-contact electrode plate and a collector press-contact electrode plate. Before using the device, a force of press, which is higher than that applied at the time of using the device and can plastically deform the thickness-correcting member, is applied to the emitter press-contact electrode plate and the collector press-contact electrode plate, thereby correcting variations in total thickness of each semiconductor chip and a corresponding one of the heat buffer plates.
    • 在本发明中,由于分别位于布置在单个平面中的IGBT芯片和FRD芯片的主表面上的热缓冲板,每个芯片的总厚度和相应的一个热量可以被设置为基本上预定的值 。 具有与芯片相对应的细长突起的厚度校正构件设置在远离芯片的热缓冲板的表面上。 在与其主表面相对的芯片的这些表面上设置有缓冲盘片。 厚度校正构件,热缓冲板和IGBT和FRD芯片被保持并同时按压在发射极压接电极板和集电体压接电极板之间。 在使用该装置之前,将加压力高于在使用该装置时施加的压力并使厚度校正构件塑性变形的压力施加到发射体压接电极板和集电体压接电极 从而校正每个半导体芯片和对应的一个热缓冲板的总厚度的变化。