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11. 发明授权

US06393509B2 Input/output device for connection and disconnection of active lines 有权
标题翻译：用于连接和断开有源线路的输入/输出设备
公开(公告)号：US06393509B2
公开(公告)日：2002-05-21
申请号：US09932973
申请日：2001-08-21
申请人： Tsutomu Yamada , Kenichi Kurosawa , Yasuo Kaminaga , Kouji Masui , Akihiro Ohashi
发明人： Tsutomu Yamada , Kenichi Kurosawa , Yasuo Kaminaga , Kouji Masui , Akihiro Ohashi
IPC分类号： G06F1300
CPC分类号： G06F13/4081 , G06F1/189 , Y02D10/14 , Y02D10/151
摘要： There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260. At the time of insertion or removal, adverse influence is not exerted on the signal transmission on the system bus, and effects of load variation on the main power supply are reduced.
摘要翻译：提供了一种输入/输出装置，其在插入或移除时对连接到系统总线的其它扩展装置没有任何不利影响。扩展装置800包括电子电路400和MOS开关300，并且被连接通过具有长和短引脚的连接器连接到系统总线（BUS）。膨胀装置800是两个电源系统，即稳定的电源250和不稳定的电源260.在插入或移除扩展装置800时，向MOS开关300提供电力和高阻抗保持电路通过一对长引脚稳定供电，为了可靠地将MOS开关300置于高阻抗状态，高阻抗保持电路350在扩展装置的内部驱动开/关控制端子，并且向来自不稳定电源260的电子电路400.在插入或移除时，不会对系统总线上的信号传输产生不利影响，并且降低对主电源的负载变化的影响。

12. 发明授权

US06289407B1 Input/output device for connection and disconnection of active lines 有权
标题翻译：用于连接和断开有源线路的输入/输出设备
公开(公告)号：US06289407B1
公开(公告)日：2001-09-11
申请号：US09499897
申请日：2000-02-08
申请人： Tsutomu Yamada , Kenichi Kurosawa , Yasuo Kaminaga , Kouji Masui , Akihiro Ohashi
发明人： Tsutomu Yamada , Kenichi Kurosawa , Yasuo Kaminaga , Kouji Masui , Akihiro Ohashi
IPC分类号： G06F1300
CPC分类号： G06F13/4081 , G06F1/189 , Y02D10/14 , Y02D10/151
摘要： There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260. At the time of insertion or removal, adverse influence is not exerted on the signal transmission on the system bus, and effects of load variation on the main power supply are reduced.
摘要翻译：提供了一种输入/输出装置，其在插入或移除时对连接到系统总线的其它扩展装置没有任何不利影响。扩展装置800包括电子电路400和MOS开关300，并且经由具有长和短引脚的连接器连接到系统总线（BUS）。膨胀装置800是两个电源系统，即稳定的电源250和不稳定的电源260.在插入或移除扩展装置800时，向MOS开关300提供电力和高阻抗保持电路通过一对长引脚稳定供电，为了可靠地将MOS开关300置于高阻抗状态，高阻抗保持电路350在扩展装置的内部驱动开/关控制端子，并且向来自不稳定电源260的电子电路400.在插入或移除时，不会对系统总线上的信号传输产生不利影响，并且降低对主电源的负载变化的影响。

13. 发明授权

US6160275A Semiconductor gate array device 失效
标题翻译：半导体门阵列器件
公开(公告)号：US6160275A
公开(公告)日：2000-12-12
申请号：US692253
申请日：1996-08-05
申请人： Yoji Nishio , Yasuo Kaminaga , Isamu Kobayashi , Yoshihiko Yamamoto , Nozomi Horino , Kousaku Hirose
发明人： Yoji Nishio , Yasuo Kaminaga , Isamu Kobayashi , Yoshihiko Yamamoto , Nozomi Horino , Kousaku Hirose
IPC分类号： H01L27/118 , H01L27/10
CPC分类号： H01L27/11807
摘要： In order to present a basic cell of a master slice type LSI having a high memory density and a high speed logic circuitry, a basic cell is composed of each pair of the PMOS 1, NMOS 4, PMOS 7, and NMOS 10, and three contact holes--besides the contact holes 17, as the contact holes within the MOS channel width W of each MOS, that are connected to the GND power lines 51 and 53, or the Vcc power lines 50 and 52--are formed in the direction perpendicular to each of the power lines. Additionally, in order to present a semiconductor integrated device having a static type RAM that has realized with its simple structure a shortening of the memory cycle, a RAM is constructed by having memory cells, in which each is composed of a pair of transfer MOSFETs, which both of the MOSFETs are turned on during the write-in operation and one of the MOSFETs is turned on during the read-out operation, is located in between a complementary data line and an input/output node that has a complementary relationship with an information storage part comprised by a pair of inverter circuits in which the inputs and outputs are mutually cross-connected. By constructing in this way, it becomes possible to speed up the write-in operation with accuracy by having a complementary write-in signal received from a pair of the complementary lines during the read-out operation, and it becomes possible to obtain read-out signals rapidly and to prevent write-in errors caused by the pre-read-out potential of the data line because the information storage part is connected only to one of the data lines through one of the transfer gates during the read-out operation.
摘要翻译：为了呈现具有高存储密度和高速逻辑电路的主片式LSI的基本单元，基本单元由每对PMOS 1，NMOS 4，PMOS 7和NMOS 10组成，并且三个接触孔 - 除了接触孔17之外，因为连接到GND电源线51和53或Vcc电源线50和52的每个MOS的MOS沟道宽度W内的接触孔形成在垂直方向上到每个电力线。此外，为了呈现具有通过其简单结构实现的具有简化结构的静态型RAM的半导体集成器件，缩短了存储器周期，RAM通过具有存储单元构成，其中每个存储单元由一对转移MOSFET组成，其中两个MOSFET在写入操作期间导通，并且在读出操作期间MOSFET中的一个导通，位于互补数据线与具有互补关系的输入/输出节点之间信息存储部分由输入和输出相互交叉连接的一对反相器电路组成。通过以这种方式构造，可以通过在读出操作期间具有从一对互补线接收的互补写入信号来准确地加速写入操作，并且可以获得读取操作，并且防止由于数据线的预读出电位引起的写入错误，因为信息存储部分在读出操作期间仅通过一个传输门连接到一条数据线。

14. 发明授权

US5880602A Input and output buffer circuit 失效
标题翻译：输入和输出缓冲电路
公开(公告)号：US5880602A
公开(公告)日：1999-03-09
申请号：US608566
申请日：1996-02-28
申请人： Yasuo Kaminaga , Yoji Nishio
发明人： Yasuo Kaminaga , Yoji Nishio
IPC分类号： H01L27/04 , H01L21/822 , H03K19/003 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/00315
摘要： An input and output buffer circuit which is contained in a first circuit operated on a first power source of a first voltage level Vcc1 and is permitted to connect to a second circuit operated on a second power source of a second voltage level Vcc2 higher than the first voltage level Vcc1 including: a driver PMOS transistor with a CMOS gate; a PAD terminal serving as an input and output terminal; and means for controlling the potential of the N well of the driver PMOS transistor in such a manner that when the potential at the PAD terminal is less than Vcc1-Vth, wherein Vth is a threshold voltage of a MOS transistor contained between the driver PMOS transistor and the PAD terminal, the potential of the N well is set at the first voltage level Vcc1; when the potential at the PAD terminal is more than Vcc1+Vth, the potential of the N well is equated with the potential at the PAD terminal; and when the input and output buffer circuit is in the output mode the potential of the N well is switched to the first voltage level Vcc1, whereby the noise resistance and the latch-up resistance of the input and output buffer circuit are improved while preventing a path current flowing through the driver PMOS transistor.
摘要翻译：一种输入和输出缓冲器电路，其被包含在第一电路Vcc1的第一电源上操作的第一电路中，并被允许连接到第二电路上的第二电路，该第二电路的第二电压电平Vcc2高于第一电压电压电平Vcc1包括：具有CMOS栅极的驱动器PMOS晶体管; 作为输入输出端子的PAD端子; 以及用于以这样的方式控制驱动器PMOS晶体管的N阱的电位的装置，即当PAD端子处的电位小于Vcc1-Vth时，其中Vth是包含在驱动器PMOS晶体管之间的MOS晶体管的阈值电压和PAD端子，将N阱的电位设定在第一电压电平Vcc1; 当PAD端子的电位大于Vcc1 + Vth时，N阱的电位等于PAD端子的电位; 并且当输入和输出缓冲器电路处于输出模式时，N阱的电位被切换到第一电压电平Vcc1，从而改善输入和输出缓冲电路的噪声电阻和闩锁电阻，同时防止流过驱动器PMOS晶体管的路径电流。

15. 发明授权

US5663659A Semiconductor integrated circuit device comprising CMOS transistors and differentiator 失效
标题翻译：包括CMOS晶体管和微分器的半导体集成电路器件
公开(公告)号：US5663659A
公开(公告)日：1997-09-02
申请号：US488441
申请日：1995-06-07
申请人： Yasuo Kaminaga , Yoji Nishio , Akihiro Tamba , Yutaka Kobayashi , Masataka Minami
发明人： Yasuo Kaminaga , Yoji Nishio , Akihiro Tamba , Yutaka Kobayashi , Masataka Minami
IPC分类号： H01L27/06 , H03K19/013 , H03K19/01
CPC分类号： H01L27/0623 , H03K19/0136
摘要： The semiconductor IC device has a circuit arrangement constituted by a first CMOS logic gate having input and output terminals, and a second CMOS logic gate which performs the same logic operation as that of the first CMOS logic gate and which has an input terminal connected to the input terminal of the first CMOS logic gate. The arrangement also requires a differentiator circuit which has an input terminal thereof connected to an output terminal of the second CMOS logic gate and has an output terminal connected to the output terminal of the first CMOS logic gate. With such an arrangement, the dependency of the effective gate propagation delay time on an output load is lowered. As a result, therefore, the arrangement can be effected using a low power supply voltage while securing a high operation speed as well as a low power consumption. The CMOS logic gates can also be facilitated in combination with NPN bipolar transistors which are connected therewith in an emitter follower circuit form. This type of arrangement is used to effect a BiNMOS type of logic (inverter) circuit. In accordance with another structural scheme, in place of the first CMOS logic gate, a BiCMOS type of arrangement is effected in combination with the second CMOS logic gate and differentiator.
摘要翻译：半导体IC器件具有由具有输入和输出端子的第一CMOS逻辑门和与第一CMOS逻辑门执行相同逻辑运算的第二CMOS逻辑门构成的电路装置，该第二CMOS逻辑门的输入端连接到第一个CMOS逻辑门的输入端。该装置还需要一个其输入端连接到第二CMOS逻辑门的输出端并具有连接到第一CMOS逻辑门的输出端的输出端的微分电路。通过这样的布置，有效栅极传播延迟时间对输出负载的依赖性降低。结果，因此，可以在确保高操作速度以及低功耗的同时，使用低电源电压来实现该配置。 CMOS逻辑门也可以与以射极跟随器电路形式连接的NPN双极晶体管结合起来。这种类型的布置用于实现BiNMOS类型的逻辑（逆变器）电路。根据另一结构方案，代替第一CMOS逻辑门，与第二CMOS逻辑门和微分器结合实现BiCMOS类型的布置。

16. 发明授权

US5614848A High-speed semiconductor integrated circuit device composed of CMOS and bipolar transistors 失效
标题翻译：由CMOS和双极晶体管组成的高速半导体集成电路器件
公开(公告)号：US5614848A
公开(公告)日：1997-03-25
申请号：US482570
申请日：1995-06-07
申请人： Yasuo Kaminaga , Yoji Nishio , Akihiro Tamba , Yutaka Kobayashi , Masataka Minami
发明人： Yasuo Kaminaga , Yoji Nishio , Akihiro Tamba , Yutaka Kobayashi , Masataka Minami
IPC分类号： H01L27/06 , H03K19/013 , H03K19/01
CPC分类号： H01L27/0623 , H03K19/0136
摘要： The semiconductor IC device has a circuit arrangement in which one or more of the circuits, such as on a single substrate, include a totem-pole series connection of bipolar transistors which are driven by arrangements of complementary MOS circuits in a manner such that high-speed logic/switching operation is effected. Arrangements of circuits can also be effected in which the totem-pole series connection is constituted by a PNP transistor, on the power source terminal side, and an NPN or NMOS transistor on the ground or pull-down side thereof. With such configurations, the output signal swing at low operating voltages can be maximized while achieving the same with reduced propagation delay time and low power consumption. The device can also be implemented by circuitry employing capacitance bootstrapping effect as well as IIL (I.sup.2 L) design schemes.
摘要翻译：半导体IC器件具有这样的电路结构，其中一个或多个电路，例如在单个衬底上，包括由互补MOS电路的布置驱动的双极晶体管的图腾柱串联连接，实现速度逻辑/切换操作。还可以实现电路的布置，其中图腾柱串联连接由在电源端侧的PNP晶体管，以及在其接地或下拉侧上的NPN或NMOS晶体管构成。通过这样的配置，可以在低工作电压下的输出信号摆幅最大化，同时实现相同的传播延迟时间和低功耗。该装置还可以通过使用电容自举效应的电路以及IIL（I2L）设计方案来实现。

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