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11. 发明申请

US20050275941A1 Metal-filled openings for submicron devices and methods of manufacture thereof 有权
标题翻译：用于亚微米器件的金属填充开口及其制造方法
公开(公告)号：US20050275941A1
公开(公告)日：2005-12-15
申请号：US10854061
申请日：2004-05-26
申请人： Chi-Wen Liu , Jung-Chih Tsao , Shih-Tzung Chang , Ying-Lang Wang , Kei-Wei Chen
发明人： Chi-Wen Liu , Jung-Chih Tsao , Shih-Tzung Chang , Ying-Lang Wang , Kei-Wei Chen
IPC分类号： G02B23/00 , H01L21/768 , H01L21/82
CPC分类号： H01L21/7684 , H01L21/76877
摘要： A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.
摘要翻译：在半导体或其他亚微米器件衬底中形成填充金属的开口的方法包括在衬底表面和开口中形成导电体层，其中导电体层具有第一晶粒尺寸。导电盖层形成在导电体层之上，导电盖层具有基本上小于第一晶粒尺寸的第二晶粒尺寸。导电体和盖层中的至少一个然后被平坦化以形成基本上与衬底表面重合的平坦表面。

12. 发明授权

US07417321B2 Via structure and process for forming the same 有权
标题翻译：通过结构及其形成方法
公开(公告)号：US07417321B2
公开(公告)日：2008-08-26
申请号：US11323484
申请日：2005-12-30
申请人： Jung-Chih Tsao , Kei-Wei Chen , Ying-Jing Lu , Yu-Sheng Wang , Yu-Ku Lin
发明人： Jung-Chih Tsao , Kei-Wei Chen , Ying-Jing Lu , Yu-Sheng Wang , Yu-Ku Lin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76846 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.
摘要翻译：通过半导体产品互连的结构和工艺流程。提供底部金属层以表示半导体产品中的连接层。底部金属层上的隔离层包括露出底部金属层的一部分的通孔。通孔包括侧壁和底部。第一阻挡金属层设置在通孔的侧壁上，但不设置在通孔的底部。在通孔的底部和第一阻挡金属层上形成金属底层。在金属底层上形成第二阻挡金属层。金属填充层填充通孔。金属底层和第二阻挡金属层之间的晶格失配小于约5％。

13. 发明申请

US20070152342A1 Via structure and process for forming the same 有权
标题翻译：通过结构及其形成方法
公开(公告)号：US20070152342A1
公开(公告)日：2007-07-05
申请号：US11323484
申请日：2005-12-30
申请人： Jung-Chih Tsao , Kei-Wei Chen , Ying-Jing Lu , Yu-Sheng Wang , Yu-Ku Lin
发明人： Jung-Chih Tsao , Kei-Wei Chen , Ying-Jing Lu , Yu-Sheng Wang , Yu-Ku Lin
IPC分类号： H01L23/52
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76846 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.
摘要翻译：通过半导体产品互连的结构和工艺流程。提供底部金属层以表示半导体产品中的连接层。底部金属层上的隔离层包括露出底部金属层的一部分的通孔。通孔包括侧壁和底部。第一阻挡金属层设置在通孔的侧壁上，但不设置在通孔的底部。在通孔的底部和第一阻挡金属层上形成金属底层。在金属底层上形成第二阻挡金属层。金属填充层填充通孔。金属底层和第二阻挡金属层之间的晶格失配小于约5％。

14. 发明申请

US20090127097A1 Forming Seed Layer in Nano-Trench Structure Using Net Deposition and Net Etch 审中-公开
标题翻译：使用净沉积和净蚀刻在纳米沟槽结构中形成种子层
公开(公告)号：US20090127097A1
公开(公告)日：2009-05-21
申请号：US11941435
申请日：2007-11-16
申请人： Kei-Wei Chen , Shih-Ho Lin , Yu-Sheng Wang , Szu-An Wu , Ying-Lang Wang
发明人： Kei-Wei Chen , Shih-Ho Lin , Yu-Sheng Wang , Szu-An Wu , Ying-Lang Wang
IPC分类号： C23C14/00
CPC分类号： C23C14/345 , C23C14/046 , H01L21/76862 , H01L21/76873
摘要： A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a net deposition step to form a seed layer having a portion in the opening, wherein the net deposition step comprises a first deposition and a first etching; performing a net etch step to the seed layer, wherein the net etch step comprises a first etching and a first deposition, wherein a portion of the seed layer remains after the net etch step; and growing a conductive material on the seed layer to fill a remaining portion of the opening.
摘要翻译：形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行净沉积步骤以形成具有在开口中的一部分的种子层，其中所述净沉积步骤包括第一沉积和第一蚀刻; 对所述种子层进行净蚀刻步骤，其中所述净蚀刻步骤包括第一蚀刻和第一沉积，其中所述种子层的一部分在所述净蚀刻步骤之后保留; 以及在种子层上生长导电材料以填充开口的剩余部分。

15. 发明授权

US08470390B2 Oxidation-free copper metallization process using in-situ baking 有权
标题翻译：无氧化铜金属化工艺采用原位烘烤
公开(公告)号：US08470390B2
公开(公告)日：2013-06-25
申请号：US11972785
申请日：2008-01-11
申请人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
IPC分类号： B05D5/12 , C23C14/00
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76828 , H01L21/76843
摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer.
摘要翻译：形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。金属特征的至少一部分通过开口露出。相应地，在金属特征的暴露部分上形成氧化物层。该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层。

16. 发明申请

US20090181164A1 Oxidation-Free Copper Metallization Process Using In-situ Baking 有权
标题翻译：使用原位烘烤的无氧铜金属化工艺
公开(公告)号：US20090181164A1
公开(公告)日：2009-07-16
申请号：US11972785
申请日：2008-01-11
申请人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
IPC分类号： H05K3/46
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76828 , H01L21/76843
摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer
摘要翻译：形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。金属特征的至少一部分通过开口露出。相应地，在金属特征的暴露部分上形成氧化物层。该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层

17. 发明申请

US20100230815A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100230815A1
公开(公告)日：2010-09-16
申请号：US12785618
申请日：2010-05-24
申请人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin
发明人： Jung-Chih Tsao , Kei-Wei Chen , Yu-Ku Lin
IPC分类号： H01L23/522 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76807 , H01L21/76832 , H01L21/76844 , H01L21/76846 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer.
摘要翻译：半导体器件及其制造方法。示例性器件包括衬底，电介质层，保护层和共形阻挡层。电介质层覆盖在衬底上并且包括开口。开口包括下部和较宽的上部，暴露基底的部分。上部的底部作为开口的肩部。保护层覆盖开口的至少一个肩部。共形阻挡层设置在开口中并覆盖保护层和电介质层，其中保护层对惰性气体等离子体的耐蚀性高于阻挡层的抗蚀性。

18. 发明授权

US07208404B2 Method to reduce Rs pattern dependence effect 有权
标题翻译：减少Rs模式依赖效应的方法
公开(公告)号：US07208404B2
公开(公告)日：2007-04-24
申请号：US10687183
申请日：2003-10-16
申请人： Jung-Chih Tsao , Chi-Wen Li , Kei-Wei Chen , Jye-Wei Hsu , Hsien-Pin Fong , Steven Lin , Ray Chuang
发明人： Jung-Chih Tsao , Chi-Wen Li , Kei-Wei Chen , Jye-Wei Hsu , Hsien-Pin Fong , Steven Lin , Ray Chuang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , H01L21/288 , H01L21/7684
摘要： A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2≦t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)≧GD2 for the second copper layer.
摘要翻译：描述了在图案内的开口中形成铜互连的方法。铜互连具有几乎独立于开口宽度和图案密度的Rs。通过沉积铜并执行第一CMP步骤，在电介质层中的通孔或沟槽中形成具有凹上表面和厚度t 1的第一铜层。具有厚度为2 的第二铜层，其中具有凸下表面的第二铜层沉积在第一铜层上通过选择性电镀方法。对第一和第二铜层进行退火，然后第二CMP步骤将第二铜层平坦化成与电介质层共面。本发明也是由上述铜层构成的铜布线，其中第一铜层具有第二铜层的晶粒密度（G SUB D1）= G D2 D2。

19. 发明申请

US20050118808A1 Method of reducing the pattern effect in the CMP process 有权
标题翻译：降低CMP工艺中图案效果的方法
公开(公告)号：US20050118808A1
公开(公告)日：2005-06-02
申请号：US10724201
申请日：2003-12-01
申请人： Chi-Wen Liu , Jung-Chih Tsao , Shien-Ping Feng , Kei-Wei Chen , Shih-Chi Lin , Ray Chuang
发明人： Chi-Wen Liu , Jung-Chih Tsao , Shien-Ping Feng , Kei-Wei Chen , Shih-Chi Lin , Ray Chuang
IPC分类号： H01L21/302 , H01L21/321 , H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/3212 , H01L21/7684
摘要： A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.
摘要翻译：降低CMP工艺中图案效果的方法。该方法包括以下步骤：提供具有图案化介电层的半导体衬底，图案化电介质层上的阻挡层和阻挡层上的导电层; 在阻挡层被抛光之前执行第一CMP工艺以去除导电层的一部分，从而降低导电层的台阶高度; 在导电层上沉积与导电层基本相同的材料层; 以及执行第二CMP工艺以暴露所述电介质层。还提供了在CMP处理和CMP返工方法之后消除凹陷现象的方法。

20. 发明授权

US07183199B2 Method of reducing the pattern effect in the CMP process 有权
标题翻译：降低CMP工艺中图案效果的方法
公开(公告)号：US07183199B2
公开(公告)日：2007-02-27
申请号：US10724201
申请日：2003-12-01
申请人： Chi-Wen Liu , Jung-Chih Tsao , Shien-Ping Feng , Kei-Wei Chen , Shih-Chi Lin , Ray Chuang
发明人： Chi-Wen Liu , Jung-Chih Tsao , Shien-Ping Feng , Kei-Wei Chen , Shih-Chi Lin , Ray Chuang
IPC分类号： H01L21/4763
CPC分类号： H01L21/3212 , H01L21/7684
摘要： A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.
摘要翻译：降低CMP工艺中图案效果的方法。该方法包括以下步骤：提供具有图案化介电层的半导体衬底，图案化电介质层上的阻挡层和阻挡层上的导电层; 在阻挡层被抛光之前执行第一CMP工艺以去除导电层的一部分，从而降低导电层的台阶高度; 在导电层上沉积与导电层基本相同的材料层; 以及执行第二CMP工艺以暴露所述电介质层。还提供了在CMP处理和CMP返工方法之后消除凹陷现象的方法。

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