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11. 发明授权

US07778062B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US07778062B2
公开(公告)日：2010-08-17
申请号：US11761400
申请日：2007-06-12
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0042 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate as underlying the cell array for data reading and writing, wherein the variable resistance element comprises a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d” orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 形成在所述半导体衬底上的至少一个单元阵列，每个存储单元具有可变电阻元件和存取元件的堆叠结构，所述存取元件具有在十倍或更多的一定电压范围内的截止电阻值与选择状态一样高; 以及形成在半导体基板上的用于数据读写的单元阵列下面的读/写电路，其中可变电阻元件包括由包含至少两种类型的阳离子元素的复合化合物组成的记录层，至少一种阳离子元素是具有“d”轨道的过渡元素，其中电子未完全填充，相邻阳离子元素之间的最短距离为0.32nm以下。

12. 发明授权

US07750334B2 Phase change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US07750334B2
公开(公告)日：2010-07-06
申请号：US11958168
申请日：2007-12-17
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： H01L29/02
CPC分类号： G11C13/0004 , G11C5/02 , G11C7/18 , G11C13/0007 , G11C2211/4013 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wirings disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.
摘要翻译：存储器件具有半导体衬底; 多个单元阵列，堆叠在基板上方，每个单元阵列具有存储单元，每个通常连接沿着第一方向布置的多个单元的一端的位线和每个共同连接沿着第二方向布置的多个单元的另一端的字线; 在基板上形成的读/写电路，位于单元阵列下面; 第一和第二垂直布线，沿着第一方向设置在每个单元阵列的两侧，以将位线连接到读/写电路; 以及在第二方向上设置在每个单元阵列两侧的第三垂直布线，以将字线连接到读/写电路。

13. 发明申请

US20100115383A1 MEMORY DEVICE WITH AN ECC SYSTEM 失效
标题翻译：具有ECC系统的存储器件
公开(公告)号：US20100115383A1
公开(公告)日：2010-05-06
申请号：US12555507
申请日：2009-09-08
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/152 , G06F11/1068 , H03M13/1575 , H03M13/3715
摘要： A memory device has an error detection and correction system constructed on a Galois finite field. The error detection and correction system includes calculation circuits for calculating the finite field elements based on syndromes obtained from read data and searching error locations, the calculation circuits having common circuits, which are used in a time-sharing mode under the control of internal clocks.
摘要翻译：存储器件具有在伽罗瓦有限域上构造的误差检测和校正系统。误差检测和校正系统包括用于基于从读取数据和搜索误差位置获得的综合数据计算有限域元素的计算电路，所述计算电路具有在内部时钟控制下的分时模式中使用的公共电路。

14. 发明授权

US07522462B2 Sense amplifier and semiconductor memory device with the same 有权
标题翻译：感应放大器和半导体存储器件相同
公开(公告)号：US07522462B2
公开(公告)日：2009-04-21
申请号：US11563408
申请日：2006-11-27
申请人： Toshiaki Edahiro , Haruki Toda
发明人： Toshiaki Edahiro , Haruki Toda
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C16/28
摘要： A sense amplifier includes: NMOS transistors, drains thereof being coupled to output nodes, gates thereof being coupled to the output nodes, sources thereof being coupled in common to the ground potential node; PMOS transistors, drains thereof being coupled to the drains of the NMOS transistors, sources thereof being coupled to the input nodes; PMOS transistors, drains thereof being coupled to the input nodes, gates thereof being coupled to the output nodes, sources thereof being coupled to the power supply node via a current source device; and NMOS transistors disposed between the output nodes and the ground potential node to be turned on before sensing; and an equalizing transistor disposed between the output nodes.
摘要翻译：读出放大器包括：NMOS晶体管，其漏极耦合到输出节点，其栅极耦合到输出节点，其源极共同耦合到地电位节点; PMOS晶体管，其漏极耦合到NMOS晶体管的漏极，其源极耦合到输入节点; PMOS晶体管，其漏极耦合到输入节点，其栅极耦合到输出节点，其源极经由电流源装置耦合到电源节点; 并且设置在所述输出节点和所述接地电位节点之间的NMOS晶体管将在感测之前导通; 以及设置在输出节点之间的均衡晶体管。

15. 发明申请

US20080310211A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20080310211A1
公开(公告)日：2008-12-18
申请号：US12140818
申请日：2008-06-17
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C2013/0042 , G11C2213/31 , G11C2213/32 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate as underlying the cell array, wherein the variable resistance element comprises a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 形成在所述半导体衬底上的至少一个单元阵列，每个存储单元具有可变电阻元件和存取元件的堆叠结构，所述存取元件具有在十倍或更多的一定电压范围内的截止电阻值与选择状态一样高; 以及形成在半导体基板上的读/写电路，其形成在单元阵列的下方，其中可变电阻元件包括由由AxMyOz表示的第一复合化合物形成的记录层（其中“A”和“M”是每个不同的阳离子元素另一个;“O”氧;和0.5 <= x <= 1.5,0.5 <= y <= 2.5和1.5 <= z <= 4.5）和第二复合化合物，其含有至少一个过渡元素和用于容纳阳离子离子

16. 发明授权

US07459716B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US07459716B2
公开(公告)日：2008-12-02
申请号：US11761333
申请日：2007-06-11
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： H01L29/02 , G11C11/00
CPC分类号： G11C13/0007 , G11C5/02 , G11C13/0004 , G11C2213/11 , G11C2213/31 , G11C2213/34 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/147 , Y10S438/936
摘要： A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, bit lines word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings disposed to connect the bit lines to the read/write circuit; and third vertical wirings disposed to connect the word lines to the read/write circuit, wherein the memory cell includes a variable resistance element for storing as information a resistance value, which has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 单元阵列堆叠在基板上方，位线字线; 形成在半导体衬底上的读/写电路; 布置成将位线连接到读/写电路的第一和第二垂直布线; 以及第三垂直布线，用于将字线连接到读/写电路，其中存储单元包括可变电阻元件，用于存储作为信息的电阻值，该电阻值具有由AxMyOz表示的第一复合化合物形成的记录层（其中 “A”和“M”是彼此不同的阳离子元素;“O”氧; 0.5 <= x <= 1.5,0.5 <= y <= 2.5和1.5 <= z <= 4.5）和第二复合化合物含有至少一个过渡元素和用于容纳阳离子离子的空腔部位。

17. 发明申请

US20080258129A1 Phase-Change Memory Device 有权
标题翻译：相变存储器件
公开(公告)号：US20080258129A1
公开(公告)日：2008-10-23
申请号：US10507475
申请日：2003-01-10
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： H01L25/03 , G11C11/21 , H01L21/8239
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C2013/0054 , G11C2013/009 , G11C2213/71 , G11C2213/72 , G11C2213/78 , G11C2213/79 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233
摘要： A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.
摘要翻译：相变存储器件具有彼此平行延伸的多个第一布线WL，多个第二布线BL布置成与第一布线WL交叉而被分离或隔离，并且存储单元MC 被布置在第一布线WL和第二布线BL的各交叉点，并且每个布线的一端连接到第一布线WL，另一端连接到第二布线BL。存储单元MC具有可变电阻元件VR，其存储由于其结晶态和非晶态之间的相变而确定的电阻值和与可变电阻元件VR串联连接的肖特基二极管SD的信息。

18. 发明申请

US20070285969A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20070285969A1
公开(公告)日：2007-12-13
申请号：US11761738
申请日：2007-06-12
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/36
CPC分类号： G11C8/08 , G11C11/36 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/009 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/147 , H01L45/1675
摘要： A resistance change memory device including: a substrate; cell arrays stacked thereabove, each including a matrix layout of memory cells; a write circuit configured to write a pair cell constituted by two neighboring memory cells; and a read circuit configured to read complementary resistance value states of the pair cell as one bit of data, wherein the memory cell includes a variable resistance element for storing as information a resistance value, and wherein the variable resistance element has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.
摘要翻译：一种电阻变化存储器件，包括：衬底; 单元阵列堆叠在其上，每个包括存储单元的矩阵布局; 写入电路，被配置为写入由两个相邻存储器单元构成的对单元; 以及读取电路，被配置为读取所述对单元的互补电阻值状态作为数据的一位，其中所述存储单元包括用于存储作为信息的电阻值的可变电阻元件，并且其中所述可变电阻元件具有由由A M和Y M表示的第一复合化合物（其中“A”和“M”是彼此不同的阳离子元素; “O”氧;和0.5 <= x <= 1.5,0.5 <= y <= 2.5和1.5 <= z <= 4.5）和第二复合化合物，其含有至少一个过渡元素和用于容纳阳离子离子的空腔部位。

19. 发明申请

US20070285968A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20070285968A1
公开(公告)日：2007-12-13
申请号：US11761400
申请日：2007-06-12
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/36
CPC分类号： G11C13/0011 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0042 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72
摘要： A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate as underlying the cell array for data reading and writing, wherein the variable resistance element comprises a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d” orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 形成在所述半导体衬底上的至少一个单元阵列，每个存储单元具有可变电阻元件和存取元件的堆叠结构，所述存取元件具有在十倍或更多的一定电压范围内的截止电阻值与选择状态一样高; 以及形成在半导体基板上的用于数据读写的单元阵列下面的读/写电路，其中可变电阻元件包括由包含至少两种类型的阳离子元素的复合化合物组成的记录层，至少一种阳离子元素是具有“d”轨道的过渡元素，其中电子未完全填充，相邻阳离子元素之间的最短距离为0.32nm以下。

20. 发明申请

US20070285965A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20070285965A1
公开(公告)日：2007-12-13
申请号：US11761333
申请日：2007-06-11
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/36
CPC分类号： G11C13/0007 , G11C5/02 , G11C13/0004 , G11C2213/11 , G11C2213/31 , G11C2213/34 , G11C2213/55 , G11C2213/56 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/147 , Y10S438/936
摘要： A resistance change memory device including: a semiconductor substrate; cell arrays stacked above the substrate, bit lines word lines; a read/write circuit formed on the semiconductor substrate; first and second vertical wirings disposed to connect the bit lines to the read/write circuit; and third vertical wirings disposed to connect the word lines to the read/write circuit, wherein the memory cell includes a variable resistance element for storing as information a resistance value, which has a recording layer formed of a first composite compound expressed by AxMyOz (where “A” and “M” are cation elements different from each other; “O” oxygen; and 0.5≦x≦1.5, 0.5≦y≦2.5 and 1.5≦z≦4.5) and a second composite compound containing at least one transition element and a cavity site for housing a cation ion.
摘要翻译：一种电阻变化存储器件，包括：半导体衬底; 单元阵列堆叠在基板上方，位线字线; 形成在半导体衬底上的读/写电路; 布置成将位线连接到读/写电路的第一和第二垂直布线; 以及第三垂直布线，用于将字线连接到读/写电路，其中存储单元包括可变电阻元件，用于存储作为信息的电阻值，该电阻值具有由A

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