专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US06668367B2 Selective promotion for resolution enhancement techniques 有权
公开(公告)号：US06668367B2
公开(公告)日：2003-12-23
申请号：US10057309
申请日：2002-01-24
申请人： Nicolas B. Cobb , Laurence W. Grodd , George P. Lippincott , Emile Sahouria
发明人： Nicolas B. Cobb , Laurence W. Grodd , George P. Lippincott , Emile Sahouria
IPC分类号： G06F1750
CPC分类号： G03F1/36
摘要： A tool for optimizing the layout of a microdevice adds fragmentation points to polygons in a first hierarchical database layer in a manner suitable for application of a tool to apply a resolution enhancement technique (RET) such as optical and process correction (OPC). Portions of polygons in a database level that interact with polygons of a second level in the database are promoted to the second database level, and refragmented. The RET operates on the polygons of the first and second levels of the database to determine how polygons of each of the first and second levels should be adjusted, if necessary, such that the layout is optimized.

12. 发明授权

US06397372B1 Cell based parallel verification of an integrated circuit design 有权
标题翻译：集成电路设计的基于单元的并行验证
公开(公告)号：US06397372B1
公开(公告)日：2002-05-28
申请号：US09234089
申请日：1999-01-19
申请人： Zeki Bozkus , Laurence W. Grodd
发明人： Zeki Bozkus , Laurence W. Grodd
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： An EDA tool is provided with the ability to determine a cell based parallel verification order for a plurality of hierarchically organized design cells of an integrated circuit design, and the ability to verify the design cells in accordance with the cell based parallel verification order, with at least some of the design cells being verified in parallel. In one embodiment, the EDA tool is also provided with the ability to re-express a design cell of the IC design in terms of a number of newly formed intervening constituent design cells, with the new intervening constituent design cells being formed in accordance with a number of metrics profiling placements of original constituent design cells of the design cell.
摘要翻译： EDA工具具有确定集成电路设计的多个分层组织的设计单元的基于单元的并行验证顺序的能力，以及根据基于单元的并行验证顺序来验证设计单元的能力，其中在最少一些设计单元被并行验证。在一个实施例中，EDA工具还具有根据多个新形成的中间组成设计单元重新表达IC设计的设计单元的能力，新的中间组成设计单元根据对设计单元的原始组成设计单元的布局的度量的数量。

13. 发明授权

US08510690B2 Hierarchical feature extraction for electrical interaction calculations 有权
公开(公告)号：US08510690B2
公开(公告)日：2013-08-13
申请号：US12777226
申请日：2010-05-10
申请人： Thomas H. Kauth , Patrick D. Gibson , Kurt C. Hertz , Laurence W. Grodd
发明人： Thomas H. Kauth , Patrick D. Gibson , Kurt C. Hertz , Laurence W. Grodd
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

14. 发明授权

US07412675B2 Hierarchical feature extraction for electrical interaction 有权
标题翻译：电相互作用的分层特征提取
公开(公告)号：US07412675B2
公开(公告)日：2008-08-12
申请号：US11202935
申请日：2005-08-12
申请人： Thomas H. Kauth , Patrick D. Gibson , Kurt C. Hertz , Laurence W. Grodd
发明人： Thomas H. Kauth , Patrick D. Gibson , Kurt C. Hertz , Laurence W. Grodd
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译：计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素到相同的层次级别来计算电相互作用。

15. 发明授权

US06931613B2 Hierarchical feature extraction for electrical interaction calculations 有权
标题翻译：电相互作用计算的分层特征提取
公开(公告)号：US06931613B2
公开(公告)日：2005-08-16
申请号：US10180956
申请日：2002-06-24
申请人： Thomas H. Kauth , Patrick D. Gibson , Kurt C. Hertz , Laurence W. Grodd
发明人： Thomas H. Kauth , Patrick D. Gibson , Kurt C. Hertz , Laurence W. Grodd
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译：计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素到相同的层次级别来计算电相互作用。

16. 发明授权

US06381731B1 Placement based design cells injection into an integrated circuit design 有权
标题翻译：基于放置的设计单元注入集成电路设计
公开(公告)号：US06381731B1
公开(公告)日：2002-04-30
申请号：US09234030
申请日：1999-01-19
申请人： Laurence W. Grodd
发明人： Laurence W. Grodd
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： An EDA tool is provided with the ability to re-express a design cell of an IC design in terms of placements of a number of newly formed intervening constituent design cells, the IC design having a number of hierarchically organized placements of design cells. The new intervening constituent design cells is formed in accordance with a number of metrics profiling placements of the original constituent design cells of the design cell. The EDA tool is also provided with the ability to determine the metrics. In one embodiment, the metrics are weights reflective of at least edge placement activities associated with row/column coordinates of the design cell. Th EDA tool determines these weights associated with the row/column coordinates, and then uses the determined weights to select a subset of the row/column coordinates as cut line coordinates to logically partition the design cell into a number of regions. Finally, the EDA tool selectively groups contents of the selected design cell to form the new intervening constituent design cells based on the contents' relations to the formed regions. In one embodiment, the EDA tool is a design verification tool for use to verify the IC design prior to fabrication.
摘要翻译： EDA工具具有在多个新形成的中间组成设计单元的放置方面重新表达IC设计的设计单元的能力，该IC设计具有多个分层组织的设计单元布局。新的中间组成设计单元根据设计单元的原始构成设计单元的多个量度分布布局来形成。 EDA工具还具有确定指标的能力。在一个实施例中，度量是反映与设计单元的行/列坐标相关联的至少边缘放置活动的权重。 EDA工具确定与行/列坐标相关联的这些权重，然后使用确定的权重来选择行/列坐标的子集作为切线坐标，以将设计单元逻辑分割成多个区域。最后，EDA工具根据内容与形成区域的关系，选择性地组合所选择的设计单元的内容以形成新的中间组成设计单元。在一个实施例中，EDA工具是用于在制造之前验证IC设计的设计验证工具。

17. 发明授权

US09507902B2 Simultaneous multi-layer fill generation 有权
公开(公告)号：US09507902B2
公开(公告)日：2016-11-29
申请号：US13093828
申请日：2011-04-25
申请人： Eugene Anikin , Fedor G. Pikus , Laurence W. Grodd , David A. Abercrombie , John W. Stedman
发明人： Eugene Anikin , Fedor G. Pikus , Laurence W. Grodd , David A. Abercrombie , John W. Stedman
IPC分类号： G06F17/50 , G03F1/44 , H01L27/02
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.

18. 发明授权

US07716614B2 Hierarchical feature extraction for electrical interaction calculations 有权
标题翻译：电相互作用计算的分层特征提取
公开(公告)号：US07716614B2
公开(公告)日：2010-05-11
申请号：US12177018
申请日：2008-07-21
申请人： Thomas H. Kauth , Patrick D. Gibson , Kurt C. Hertz , Laurence W. Grodd
发明人： Thomas H. Kauth , Patrick D. Gibson , Kurt C. Hertz , Laurence W. Grodd
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译：计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素到相同的层次级别来计算电相互作用。

19. 发明授权

US07240321B2 Selective promotion for resolution enhancement techniques 有权
标题翻译：选择性推广分辨率增强技术
公开(公告)号：US07240321B2
公开(公告)日：2007-07-03
申请号：US10730765
申请日：2003-12-08
申请人： Nicolas B. Cobb , Laurence W. Grodd , George P. Lippincott , Emile Sahouria
发明人： Nicolas B. Cobb , Laurence W. Grodd , George P. Lippincott , Emile Sahouria
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A tool for optimizing the layout of a microdevice adds fragmentation points to polygons in a first hierarchical database layer in a manner suitable for application of a tool to apply a resolution enhancement technique (RET) such as optical and process correction (OPC). Portions of polygons in a database level that interact with polygons of a second level in the database are promoted to the second database level, and refragmented. The RET operates on the polygons of the first and second levels of the database to determine how polygons of each of the first and second levels should be adjusted, if necessary, such that the layout is optimized.
摘要翻译：用于优化微设备的布局的工具以适于应用工具以应用诸如光学和过程校正（OPC）的分辨率增强技术（RET）的方式向第一分层数据库层中的多边形添加碎片点。与数据库中第二级多边形交互的数据库级别中的多边形部分将升级到第二个数据库级别，并进行重新碎片整理。 RET对数据库的第一和第二级别的多边形进行操作，以确定如果需要，如何调整第一级和第二级中的每一级的多边形，使得布局被优化。

20. 发明授权

US06971080B2 Placement based design cells injection into an integrated circuit design 有权
标题翻译：基于放置的设计单元注入集成电路设计
公开(公告)号：US06971080B2
公开(公告)日：2005-11-29
申请号：US10135941
申请日：2002-04-29
申请人： Laurence W. Grodd
发明人： Laurence W. Grodd
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An EDA tool is provided with the ability to re-express a design cell of an IC design in terms of placements of a number of newly formed intervening constituent design cells, the IC design having a number of hierarchically organized placements of design cells. The new intervening constituent design cells is formed in accordance with a number of metrics profiling placements of the original constituent design cells of the design cell. The EDA tool is also provided with the ability to determine the metrics. In one embodiment, the metrics are weights reflective of at least edge placement activities associated with row/column coordinates of the design cell. The EDA tool determines these weights associated with the row/column coordinates, and then uses the determined weights to select a subset of the row/column coordinates as cut line coordinates to logically partition the design cell into a number of regions. Finally, the EDA tool selectively groups contents of the selected design cell to form the new intervening constituent design cells based on the contents' relations to the formed regions. In one embodiment, the EDA tool is a design verification tool for use to verify the IC design prior to fabrication.
摘要翻译： EDA工具具有在多个新形成的中间组成设计单元的放置方面重新表达IC设计的设计单元的能力，该IC设计具有多个分层组织的设计单元布局。新的中间组成设计单元根据设计单元的原始构成设计单元的多个量度分布布局来形成。 EDA工具还具有确定指标的能力。在一个实施例中，度量是反映与设计单元的行/列坐标相关联的至少边缘放置活动的权重。 EDA工具确定与行/列坐标相关联的这些权重，然后使用确定的权重来选择行/列坐标的子集作为切线坐标，以将设计单元逻辑分割成多个区域。最后，EDA工具根据内容与形成区域的关系，选择性地组合所选择的设计单元的内容以形成新的中间组成设计单元。在一个实施例中，EDA工具是用于在制造之前验证IC设计的设计验证工具。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式