会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 11. 发明申请
    • Silicon-on-insulator near infrared active pixel sensor array
    • 绝缘体上的近红外有源像素传感器阵列
    • US20070190681A1
    • 2007-08-16
    • US11352724
    • 2006-02-13
    • Jong-Jan LeeJer-Shen MaaDouglas TweetSheng Hsu
    • Jong-Jan LeeJer-Shen MaaDouglas TweetSheng Hsu
    • H01L21/00
    • H01L27/14649H01L27/14609H01L27/14689
    • A method is provided for forming a near infrared (NIR) active pixel sensor array on a silicon-on-insulator (SOI) substrate. The method forms a first wafer comprising a high resistance first Si substrate and a moderately doped first Si layer, and forms a second wafer comprising a first silicon oxide layer and a second Si layer. The method bonds the first wafer to the second wafer, forming a SOI substrate. Then, a diode is formed with a p-n junction space charge region extending into the first Si substrate. A thin-film transistor (TFT) is formed in the second Si layer, and interconnects are formed between the TFT and the diode. For example, first Si substrate may have a resistivity of greater than 100 ohm-cm, and the first Si layer may have a dopant concentration in the range of about 1×1016 to about 5×1018 cm−3.
    • 提供了一种用于在绝缘体上硅(SOI)衬底上形成近红外(NIR)有源像素传感器阵列的方法。 该方法形成包括高电阻第一Si衬底和中度掺杂的第一Si层的第一晶片,并且形成包括第一氧化硅层和第二Si层的第二晶片。 该方法将第一晶片连接到第二晶片,形成SOI衬底。 然后,形成具有延伸到第一Si衬底中的p-n结空间电荷区域的二极管。 在第二Si层中形成薄膜晶体管(TFT),并且在TFT和二极管之间形成互连。 例如,第一Si衬底可以具有大于100欧姆 - 厘米的电阻率,并且第一Si层可以具有在约1×10 16至约5×10 18范围内的掺杂剂浓度, / SUP> cm 3 -3。
    • 16. 发明申请
    • Floating body germanium phototransistor with photo absorption threshold bias region
    • 具有光吸收阈值偏置区域的浮体锗光电晶体管
    • US20070004067A1
    • 2007-01-04
    • US11261191
    • 2005-10-28
    • Sheng HsuJong-Jan LeeJer-Shen MaaDouglas Tweet
    • Sheng HsuJong-Jan LeeJer-Shen MaaDouglas Tweet
    • H01L31/00H01L21/00
    • H01L31/1136
    • A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.
    • 提出了具有光吸收阈值偏置区域的浮体锗(Ge)光电晶体管,以及相关的制造工艺。 该方法包括:提供p掺杂硅(Si)衬底; 选择性地形成覆盖在所述Si衬底的第一表面上的绝缘体层; 形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成栅极电介质,栅电极和栅极间隔物; 在Ge层中形成源极/漏极(S / D)区域; 并且在Ge层中形成邻近沟道区的光吸收阈值偏置区域。 在一个方面,第二S / D区域具有比第一S / D长度更长的长度。 光吸收阈值偏置区域位于第二S / D区域的下方。 或者,第二S / D区域与沟道分离偏移,光吸收阈值偏置区域是在光p掺杂之后的Ge层中的偏移。
    • 17. 发明申请
    • Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer
    • 将双轴拉伸应变NMOS和单轴压应变PMOS集成在同一晶圆上
    • US20060160291A1
    • 2006-07-20
    • US11039542
    • 2005-01-19
    • Jong-Jan LeeJer-Shen MaaDouglas TweetSheng Hsu
    • Jong-Jan LeeJer-Shen MaaDouglas TweetSheng Hsu
    • H01L21/8238
    • H01L29/7842H01L21/76254H01L21/823807H01L21/823814H01L21/823828H01L21/84H01L27/1203
    • A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H2+ ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer from the wafer; growing a layer of silicon; finishing a gate module; depositing a layer of SiO2 to cover the NMOS wafer; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area; wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compressive strained; and completing the CMOS device.
    • 制造用于NMOS制造的双轴拉伸应变层的方法和用于CMOS IC的单个晶片上的用于PMOS制造的单轴压缩应变层包括制备用于CMOS制造的硅衬底; 沉积,图案化和蚀刻第一和第二绝缘层; 从PMOS有源区域去除所述第二绝缘层的一部分; 在PMOS有源区上沉积一层外延硅; 从NMOS有源区域去除所述第二绝缘层的一部分; 生长外延硅层并在NMOS有源区上生长外延SiGe层; 注入H 2 O 2 + + / - +离子; 退火晶片以松弛SiGe层; 从晶片上去除剩余的第二绝缘层; 生长一层硅; 完成门模块; 沉积SiO 2层以覆盖NMOS晶片; 蚀刻PMOS有源区中的硅; 在PMOS有源区上选择性地生长SiGe层; 其中所述NMOS有源区中的硅层处于双轴拉伸应变下,并且所述PMOS有源区中的硅层是单轴压缩应变的; 并完成CMOS设备。