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11. 发明授权

US07419862B2 Method of fabricating pseudomorphic high electron mobility transistor 有权
标题翻译：制造假型高电子迁移率晶体管的方法
公开(公告)号：US07419862B2
公开(公告)日：2008-09-02
申请号：US11446750
申请日：2006-06-05
申请人： Jong Won Lim , Ho Kyun Ahn , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hea Cheon Kim
发明人： Jong Won Lim , Ho Kyun Ahn , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hea Cheon Kim
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7784 , H01L29/1029 , H01L29/66462
摘要： Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT). The method includes the steps of: preparing a substrate including a channel layer and a capping layer that is the uppermost layer; forming a source and a drain on the capping layer; forming a first protective layer on the entire surface of the resultant structure and then patterning the first protective layer to expose a portion of the capping layer in a channel region; removing the exposed portion of the capping layer to form a first recess structure; forming a second protective layer on the entire surface of the resultant structure and then patterning the second protective layer to expose a portion of the substrate in the first recess structure so that a second recess structure is formed; forming a multilayered photoresist layer on the entire surface of the resultant structure and then patterning the multilayered photoresist layer to expose a portion of the substrate through the second recess structure and form a gate-shaped opening; and depositing a metal layer to fill the gate-shaped opening and then removing the multilayered photoresist layer to form a gate connected to the substrate through the second recess structure.
摘要翻译：提供了制造假象高电子迁移率晶体管（PHEMT）的方法。该方法包括以下步骤：制备包括沟道层和作为最上层的覆盖层的衬底; 在封盖层上形成源极和漏极; 在所得结构的整个表面上形成第一保护层，然后图案化第一保护层以暴露沟道区中的覆盖层的一部分; 去除所述覆盖层的暴露部分以形成第一凹陷结构; 在所得结构的整个表面上形成第二保护层，然后构图第二保护层，以暴露第一凹陷结构中的基底的一部分，从而形成第二凹陷结构; 在所得结构的整个表面上形成多层光致抗蚀剂层，然后构图多层光致抗蚀剂层，以通过第二凹陷结构暴露出基板的一部分并形成栅极形开口; 以及沉积金属层以填充所述栅极开口，然后移除所述多层光致抗蚀剂层，以形成通过所述第二凹陷结构连接到所述衬底的栅极。

12. 发明申请

US20070134862A1 Method of fabricating pseudomorphic high electron mobility transistor 有权
标题翻译：制造假型高电子迁移率晶体管的方法
公开(公告)号：US20070134862A1
公开(公告)日：2007-06-14
申请号：US11446750
申请日：2006-06-05
申请人： Jong Won Lim , Ho Kyun Ahn , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hea Cheon Kim
发明人： Jong Won Lim , Ho Kyun Ahn , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hea Cheon Kim
IPC分类号： H01L21/8234
CPC分类号： H01L29/7784 , H01L29/1029 , H01L29/66462
摘要： Provided is a method of fabricating a pseudomorphic high electron mobility transistor (PHEMT). The method includes the steps of: preparing a substrate including a channel layer and a capping layer that is the uppermost layer; forming a source and a drain on the capping layer; forming a first protective layer on the entire surface of the resultant structure and then patterning the first protective layer to expose a portion of the capping layer in a channel region; removing the exposed portion of the capping layer to form a first recess structure; forming a second protective layer on the entire surface of the resultant structure and then patterning the second protective layer to expose a portion of the substrate in the first recess structure so that a second recess structure is formed; forming a multilayered photoresist layer on the entire surface of the resultant structure and then patterning the multilayered photoresist layer to expose a portion of the substrate through the second recess structure and form a gate-shaped opening; and depositing a metal layer to fill the gate-shaped opening and then removing the multilayered photoresist layer to form a gate connected to the substrate through the second recess structure.
摘要翻译：提供了制造假象高电子迁移率晶体管（PHEMT）的方法。该方法包括以下步骤：制备包括沟道层和作为最上层的覆盖层的衬底; 在封盖层上形成源极和漏极; 在所得结构的整个表面上形成第一保护层，然后图案化第一保护层以暴露沟道区中的覆盖层的一部分; 去除所述覆盖层的暴露部分以形成第一凹陷结构; 在所得结构的整个表面上形成第二保护层，然后构图第二保护层，以暴露第一凹陷结构中的基底的一部分，从而形成第二凹陷结构; 在所得结构的整个表面上形成多层光致抗蚀剂层，然后构图多层光致抗蚀剂层，以通过第二凹陷结构暴露出基板的一部分并形成栅极形开口; 以及沉积金属层以填充所述栅极开口，然后移除所述多层光致抗蚀剂层，以形成通过所述第二凹陷结构连接到所述衬底的栅极。

13. 发明申请

US20110143507A1 TRANSISTOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件的晶体管及其制造方法
公开(公告)号：US20110143507A1
公开(公告)日：2011-06-16
申请号：US13004750
申请日：2011-01-11
申请人： Jae Kyoung Mun , Hong Gu Ji , Ho Kyun Ahn , Hae Cheon Kim
发明人： Jae Kyoung Mun , Hong Gu Ji , Ho Kyun Ahn , Hae Cheon Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7785 , H01L29/42316
摘要： Provided are a transistor of a semiconductor device and a method of fabricating the same. The transistor of a semiconductor device includes an epitaxial substrate having a buffer layer, a first silicon (Si) planar doped layer, a first conductive layer, a second Si planar doped layer having a different dopant concentration from the first Si planar doped layer, and a second conductive layer, which are sequentially formed on a semi-insulating substrate; a source electrode and a drain electrode formed on both sides of the second conductive layer to penetrate the first Si planar doped layer to a predetermined depth to form an ohmic contact; and a gate electrode formed on the second conductive layer between the source electrode and the drain electrode to form a contact with the second conductive layer, wherein the gate electrode, the source electrode and the drain electrode are electrically insulated by an insulating layer, and a predetermined part of an upper part of the gate electrode is formed to overlap at least one of the source electrode and the drain electrode. Therefore, a maximum voltage that can be applied to the switching device is increased due to increases of a gate turn-on voltage and a breakdown voltage, and decrease of a parallel conduction component. As a result of this improved power handling capability, high-power and low-distortion characteristics and high isolation can be expected from the switching device.
摘要翻译：提供半导体器件的晶体管及其制造方法。半导体器件的晶体管包括具有缓冲层，第一硅（Si）平面掺杂层，第一导电层，具有与第一Si平面掺杂层不同的掺杂剂浓度的第二Si平面掺杂层的外延衬底，以及第二导电层，其依次形成在半绝缘基板上; 源电极和漏电极，形成在第二导电层的两侧，以将第一Si平面掺杂层穿透到预定深度以形成欧姆接触; 以及形成在所述源电极和所述漏电极之间的所述第二导电层上的栅电极，以与所述第二导电层形成接触，其中所述栅电极，所述源电极和所述漏极由绝缘层电绝缘，栅电极的上部的预定部分形成为与源电极和漏电极中的至少一个重叠。因此，由于栅极导通电压和击穿电压的增加以及并联导通分量的降低，可以施加到开关器件的最大电压增加。由于这种改进的功率处理能力，可以期望从开关器件获得高功率和低失真特性以及高隔离度。

14. 发明授权

US08697507B2 Transistor of semiconductor device and method of fabricating the same 有权
标题翻译：半导体器件的晶体管及其制造方法
公开(公告)号：US08697507B2
公开(公告)日：2014-04-15
申请号：US13004750
申请日：2011-01-11
申请人： Jae Kyoung Mun , Hong Gu Ji , Ho Kyun Ahn , Hae Cheon Kim
发明人： Jae Kyoung Mun , Hong Gu Ji , Ho Kyun Ahn , Hae Cheon Kim
IPC分类号： H01L21/338
CPC分类号： H01L29/7785 , H01L29/42316
摘要： Provided are a transistor of a semiconductor device and a method of fabricating the same. The transistor of a semiconductor device includes an epitaxial substrate having a buffer layer, a first silicon (Si) planar doped layer, a first conductive layer, a second Si planar doped layer having a different dopant concentration from the first Si planar doped layer, and a second conductive layer, which are sequentially formed on a semi-insulating substrate; a source electrode and a drain electrode formed on both sides of the second conductive layer to penetrate the first Si planar doped layer to a predetermined depth to form an ohmic contact; and a gate electrode formed on the second conductive layer between the source electrode and the drain electrode to form a contact with the second conductive layer, wherein the gate electrode, the source electrode and the drain electrode are electrically insulated by an insulating layer, and a predetermined part of an upper part of the gate electrode is formed to overlap at least one of the source electrode and the drain electrode. Therefore, a maximum voltage that can be applied to the switching device is increased due to increases of a gate turn-on voltage and a breakdown voltage, and decrease of a parallel conduction component. As a result of this improved power handling capability, high-power and low-distortion characteristics and high isolation can be expected from the switching device.
摘要翻译：提供半导体器件的晶体管及其制造方法。半导体器件的晶体管包括具有缓冲层，第一硅（Si）平面掺杂层，第一导电层，具有与第一Si平面掺杂层不同的掺杂剂浓度的第二Si平面掺杂层的外延衬底，以及第二导电层，其依次形成在半绝缘基板上; 源电极和漏电极，形成在第二导电层的两侧，以将第一Si平面掺杂层穿透到预定深度以形成欧姆接触; 以及形成在所述源电极和所述漏电极之间的所述第二导电层上的栅电极，以与所述第二导电层形成接触，其中所述栅电极，所述源电极和所述漏极由绝缘层电绝缘，栅电极的上部的预定部分形成为与源电极和漏电极中的至少一个重叠。因此，由于栅极导通电压和击穿电压的增加以及并联导通分量的降低，可以施加到开关器件的最大电压增加。由于这种改进的功率处理能力，可以期望从开关器件获得高功率和低失真特性以及高隔离度。

15. 发明授权

US08294521B2 Power amplifier having depletion mode high electron mobility transistor 有权
标题翻译：具有耗尽型高电子迁移率晶体管的功率放大器
公开(公告)号：US08294521B2
公开(公告)日：2012-10-23
申请号：US12855055
申请日：2010-08-12
申请人： Dong Min Kang , Hong Gu Ji , Hokyun Ahn , Jong-Won Lim , Woojin Chang , Sang-Heung Lee , Dong-Young Kim , Hae Cheon Kim
发明人： Dong Min Kang , Hong Gu Ji , Hokyun Ahn , Jong-Won Lim , Woojin Chang , Sang-Heung Lee , Dong-Young Kim , Hae Cheon Kim
IPC分类号： H03F3/04
CPC分类号： H03F3/24 , H03F1/565 , H03F3/195 , H03F2200/222
摘要： Provided is a power amplifier including: a depletion mode high electron mobility transistor (D-mode HEMT) configured to amplify a signal inputted to a gate terminal and output the amplified signal through a drain terminal; an input matching circuit configured to serially ground the gate terminal; and a DC bias circuit connected between the drain terminal and a ground. Through the foregoing configuration, the HEMT may be biased only by a single DC bias circuit without any biasing means to provide a negative voltage. Also, superior matching characteristic may be provided in various operation frequency bands through a shunt inductor and a choke inductor.
摘要翻译：提供了一种功率放大器，包括：耗尽型高电子迁移率晶体管（D模式HEMT），被配置为放大输入到栅极端子的信号，并通过漏极端子输出放大的信号; 输入匹配电路，被配置为使所述栅极端子串联接地; 以及连接在漏极端子和地之间的DC偏置电路。通过上述配置，HEMT可以仅由单个DC偏置电路偏压而没有任何偏置装置来提供负电压。此外，可以通过并联电感器和扼流电感器在各种工作频带中提供优异的匹配特性。

16. 发明授权

US07933576B2 Sub-harmonic mixer 失效
标题翻译：次谐波混频器
公开(公告)号：US07933576B2
公开(公告)日：2011-04-26
申请号：US11946315
申请日：2007-11-28
申请人： Hong Gu Ji , Hae Cheon Kim , Hyun Kyu Yu
发明人： Hong Gu Ji , Hae Cheon Kim , Hyun Kyu Yu
IPC分类号： H04B1/16
CPC分类号： H03D7/1425 , H03D7/1433 , H03D7/1441 , H03D7/1475 , H03D2200/0043
摘要： A sub-harmonic mixer is provided, which includes: a mixer core having first and second transistors performing switching operations in response to a local oscillator (LO) signal and a radio frequency (RF) signal; a power source applying bias maximizing nonlinearity of a transistor included in the mixer core; an RF port applying an RF signal to the mixer core; an LO port applying an LO signal to the mixer core; and first and second phase delay circuits in which the RF signals applied to the first and second transistors have a 180-degree phase difference.
摘要翻译：提供了一种亚谐波混频器，其包括：具有第一和第二晶体管的混频器核，其响应于本地振荡器（LO）信号和射频（RF）信号执行切换操作; 施加偏置最大化混合器核心中包括的晶体管的非线性的电源; 将RF信号施加到混频器核心的RF端口; LO端口将LO信号施加到混频器核心; 以及施加到第一和第二晶体管的RF信号具有180度相位差的第一和第二相位延迟电路。

17. 发明授权

US06933543B2 Compound semiconductor high frequency switch device 有权
标题翻译：复合半导体高频开关器件
公开(公告)号：US06933543B2
公开(公告)日：2005-08-23
申请号：US10874396
申请日：2004-06-22
申请人： Jae Kyoung Mun , Hong Gu Ji , Hokyun Ahn , Heacheon Kim
发明人： Jae Kyoung Mun , Hong Gu Ji , Hokyun Ahn , Heacheon Kim
IPC分类号： H01L27/095 , H01L29/739 , H01L29/778 , H01L31/072
CPC分类号： H01L29/7785
摘要： A high frequency switch device includes an epitaxy substrate that is formed by sequentially stacking an AlGaAs/GaAs superlattic buffer layer, a first Si planar doping layer, an undoped first AlGaAs spacer, an undoped InGaAs layer, an undoped second AlGaAs spacer, a second Si planar doping layer having a doping density greater than that of the first Si planar doping layer, and an undoped GaAs/AlGaAs capping layer on a GaAs semi-insulated substrate. The undoped GaAs/AlGaAs capping layer is formed with a source electrode and a drain electrode that form an ohmic contact with the undoped GaAs/AlGaAs capping layer thereon, and a gate electrode formed between the source electrode and the drain electrode, thereby forming a Schottky contact with the undoped GaAs/AlGaAs capping layer.
摘要翻译：高频开关器件包括：通过依次层叠AlGaAs / GaAs超缓冲层，第一Si平面掺杂层，未掺杂的第一AlGaAs间隔物，未掺杂的InGaAs层，未掺杂的第二AlGaAs间隔物，第二Si 具有大于第一Si平面掺杂层的掺杂密度的平坦掺杂层和GaAs半绝缘衬底上的未掺杂的GaAs / AlGaAs覆盖层。未掺杂的GaAs / AlGaAs覆盖层形成有与其上的未掺杂的GaAs / AlGaAs覆盖层形成欧姆接触的源电极和漏电极，以及形成在源电极和漏电极之间的栅电极，由此形成肖特基与未掺杂的GaAs / AlGaAs覆盖层接触。

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