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11. 发明授权

US6151664A Programmable SRAM and DRAM cache interface with preset access priorities 有权
标题翻译：可编程SRAM和DRAM缓存接口，具有预设的访问优先级
公开(公告)号：US6151664A
公开(公告)日：2000-11-21
申请号：US329134
申请日：1999-06-09
申请人： John Michael Borkenhagen , Gerald Gregory Fagerness , John David Irish , David John Krolak
发明人： John Michael Borkenhagen , Gerald Gregory Fagerness , John David Irish , David John Krolak
IPC分类号： G06F12/00 , G06F12/06 , G06F12/08 , G06F13/18
CPC分类号： G06F12/0893
摘要： A cache interface that supports both Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is disclosed. The cache interface preferably comprises two portions, one portion on the processor and one portion on the cache. A designer can simply select which RAM he or she wishes to use for a cache, and the cache controller interface portion on the processor configures the processor to use this type of RAM. The cache interface portion on the cache is simple when being used with DRAM in that a busy indication is asserted so that the processor knows when an access collision occurs between an access generated by the processor and the DRAM cache. An access collision occurs when the DRAM cache is unable to read or write data due to a precharge, initialization, refresh, or standby state. When the cache interface is used with an SRAM cache, the busy indication is preferably ignored by a processor and the processor's cache interface portion. Additionally, the disclosed cache interface allows speed and size requirements for the cache to be programmed into the interface. In this manner, the interface does not have to be redesigned for use with different sizes or speeds of caches.
摘要翻译：公开了一种支持静态随机存取存储器（SRAM）和动态随机存取存储器（DRAM）的缓存接口。高速缓存接口优选地包括两个部分，处理器上的一个部分和高速缓存上的一个部分。设计人员可以简单地选择他或她希望用于高速缓存的RAM，并且处理器上的高速缓存控制器接口部分使处理器使用这种类型的RAM。当与DRAM一起使用时，缓存上的高速缓存接口部分是简单的，因为忙指示被断言，使得处理器知道在由处理器生成的访问与DRAM高速缓存之间何时发生访问冲突。当DRAM高速缓存由于预充电，初始化，刷新或待机状态而无法读取或写入数据时，发生访问冲突。当高速缓存接口与SRAM缓存一起使用时，处理器和处理器的高速缓存接口部分最好忽略忙指示。此外，所公开的高速缓存接口允许高速缓存的速度和大小要求被编程到接口中。以这种方式，界面不必重新设计用于不同大小或速度的高速缓存。

12. 发明授权

US08151265B2 Apparatus for and method for real-time optimization of virtual machine input/output performance 有权
标题翻译：用于实时优化虚拟机输入/输出性能的装置和方法
公开(公告)号：US08151265B2
公开(公告)日：2012-04-03
申请号：US11959473
申请日：2007-12-19
申请人： Shmuel Ben-Yehuda , John Michael Borkenhagen
发明人： Shmuel Ben-Yehuda , John Michael Borkenhagen
IPC分类号： G06F9/46 , G06F9/455 , G06F3/00 , G06F13/00
CPC分类号： G06F9/545 , G06F9/45558 , G06F2009/45579
摘要： The present invention implements a mechanism to decide when it is beneficial to switch from the current virtual input/output mechanism to a different one. The present invention determines which input/output mechanism each virtual machine should use based on the available input/output resources of the virtual machines (with their respective available input/output adapters), the number of virtual machines running and their input/output needs, and the input/output needs of the virtual machine being considered. The present invention also provides a mechanism for virtual machine to seamlessly switch input/output mechanisms. When beneficial, the standard hot-plug mechanism of the virtual machine and the hypervisor is used to first remove the existing input/output mechanism and then add the new input/output mechanism.
摘要翻译：本发明实现了一种机制，用于决定什么时候从当前的虚拟输入/输出机制切换到不同的虚拟输入/输出机制是有益的。本发明基于虚拟机（其各自的可用输入/输出适配器）的可用输入/输出资源，运行的虚拟机的数量及其输入/输出需求来确定每个虚拟机应该使用哪个输入/输出机制，并考虑虚拟机的输入/输出需求。本发明还提供了一种用于虚拟机无缝切换输入/输出机制的机制。有利的是，使用虚拟机和管理程序的标准热插拔机制来首先删除现有的输入/输出机制，然后添加新的输入/输出机制。

13. 发明授权

US07921264B2 Dual-mode memory chip for high capacity memory subsystem 有权
标题翻译：用于高容量存储器子系统的双模存储芯片
公开(公告)号：US07921264B2
公开(公告)日：2011-04-05
申请号：US11769011
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0607 , G06F13/1694 , Y02D10/13 , Y02D10/14
摘要： A dual-mode memory chip supports a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.
摘要翻译：双模存储器芯片支持第一操作模式，其中接收的数据访问命令包含芯片选择数据以识别由命令寻址的芯片，并且存储器芯片中的控制逻辑确定命令是否寻址到芯片，第二操作模式操作模式，其中所接收的数据访问命令寻址一组多个芯片。优选地，第一模式支持存储芯片的菊花链配置。优选地，第二模式支持分层交错存储器子系统，其中每个可寻址的芯片集合被配置为树，命令和写入数据在树下传播，在树的每个后续级别增加的码片数量。

14. 发明授权

US07809913B2 Memory chip for high capacity memory subsystem supporting multiple speed bus 有权
标题翻译：支持多速总线的高容量内存子系统的内存芯片
公开(公告)号：US07809913B2
公开(公告)日：2010-10-05
申请号：US11769006
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F13/18
CPC分类号： G06F13/4243
摘要： A memory module contains an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.
摘要翻译：存储器模块包含用于从外部源接收存储器访问命令的接口，其中接口的第一部分以第一总线频率接收存储器访问数据，并且接口的第二部分以第二不同总线频率接收存储器访问数据。优选地，存储器模块包含第二接口，用于重新传输也以双频操作的存储器访问数据。存储器模块优选地用于以树形结构组织的高容量存储器子系统，其中数据访问是交错的。优选地，存储器模块具有多模式操作，其中之一支持用于接收和重新传送数据访问命令的不同部分的双速总线，另一个支持常规的菊花链。

15. 发明申请

US20090300411A1 Implementing Redundant Memory Access Using Multiple Controllers for Memory System 审中-公开
标题翻译：使用多个控制器实现对存储器系统的冗余内存访问
公开(公告)号：US20090300411A1
公开(公告)日：2009-12-03
申请号：US12132120
申请日：2008-06-03
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , William Paul Hovis , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , William Paul Hovis , Mark Owen Maxson
IPC分类号： G06F11/14
CPC分类号： G06F11/1666 , G06F11/2092
摘要： A method and apparatus implement redundant memory access using multiple controllers for a memory system, and a design structure on which the subject circuit resides are provided. A first memory controller uses a first memory and a second memory controller uses the second memory as its respective primary address space, for storage and fetches. The second memory controller is also connected to the first memory. The first memory controller is also connected to the second memory. The first memory controller and the second memory controller, for example, are connected together by a processor communications bus. When one of the first memory controller or the second memory controller fails, then the other memory controller is notified. The other memory controller takes control of the memory for the failed controller, using the direct connection to that memory, and maintains coherence of both the first memory and second memory.
摘要翻译：一种使用存储系统的多个控制器实现冗余存储器访问的方法和装置，以及设置有主题电路所在的设计结构。第一存储器控制器使用第一存储器，并且第二存储器控制器使用第二存储器作为其相应的主地址空间，用于存储和提取。第二存储器控制器也连接到第一存储器。第一存储器控制器也连接到第二存储器。例如，第一存储器控制器和第二存储器控制器通过处理器通信总线连接在一起。当第一个存储器控制器或第二个存储器控制器中的一个发生故障时，则通知另一个存储器控制器。另一个存储器控制器使用与该存储器的直接连接来控制故障控制器的存储器，并保持第一存储器和第二存储器的相干性。

16. 发明授权

US07620763B2 Memory chip having an apportionable data bus 有权
标题翻译：具有可分配数据总线的存储芯片
公开(公告)号：US07620763B2
公开(公告)日：2009-11-17
申请号：US11459943
申请日：2006-07-26
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , Andrew Benson Maki , Mark Owen Maxson
IPC分类号： G06F13/40 , G06F13/28
CPC分类号： G06F13/4243
摘要： A memory chip having a data bus having a plurality of bits. The number of bits is apportioned between a read portion and a write portion. The write portion is dedicated to receiving data that is to be written into an array on the memory chip; the read portion is dedicated to driving data that has been read from the array on the memory chip. The apportionment is programmable. Apportionment can be specified by programming signal pins on the memory chip, connecting the signal pins to appropriate logical values. The apportionment can alternatively be specified by scanning apportionment information into the memory chip at bring up time. The apportionment and also alternatively be specified by receiving apportionment information in an address/command word.
摘要翻译：一种具有数据总线的存储器芯片，具有多个位。比特数在读取部分和写入部分之间分配。写入部分专用于接收要写入存储器芯片中的阵列的数据; 读取部分专用于驱动已经从存储器芯片上的阵列读取的数据。分配是可编程的。分配可以通过编程存储器芯片上的信号引脚指定，将信号引脚连接到适当的逻辑值。可以通过在启动时间内将分配信息扫描到存储器芯片来指定分配。分配也可以通过在地址/命令字中接收分配信息来指定。

17. 发明授权

US07468993B2 Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces 有权
标题翻译：动态重构固态存储器件，通过多个数据接口复制和定时复用数据
公开(公告)号：US07468993B2
公开(公告)日：2008-12-23
申请号：US11035555
申请日：2005-01-14
申请人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Paul Rudrud
发明人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Paul Rudrud
IPC分类号： H04J3/02
CPC分类号： G11C7/1051 , G11C7/1012 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C7/1093 , G11C7/1096 , G11C29/022 , G11C2029/0409
摘要： Multiple interfaces dedicated to individual logic circuits such as memory arrays are capable of being dynamically reconfigured from operating separately and in parallel to operating in a more collective manner to ensure that data associated with all of the logic circuits will be communicated irrespective of a failure in any of the interfaces. Specifically, a plurality of interfaces, each of which being ordinarily configured to communicate data associated with an associated logic circuit in parallel with the other interfaces, may be dynamically reconfigured, e.g., in response to a detected failure in one or more of the interfaces, to communicate data associated with each of the interfaces over each of at least a subset of the interfaces in a time multiplexed and replicated manner.
摘要翻译：专用于各个逻辑电路（例如存储器阵列）的多个接口能够被动态地重新配置，以独立运行并行并行地以更集体的方式运行，以确保与所有逻辑电路相关联的数据将被传送，而不管任何的接口。具体地，可以动态地重新配置多个接口，每个接口通常被配置为与其他接口并行地传送与相关逻辑电路相关联的数据，例如响应于一个或多个接口中检测到的故障，以时间复用和复制的方式在接口的至少一个子集中的每一个上传送与每个接口相关联的数据。

18. 发明授权

US07467260B2 Method and apparatus to purge remote node cache lines to support hot node replace in a computing system 有权
标题翻译：清除远程节点缓存行以支持计算系统中的热节点替换的方法和装置
公开(公告)号：US07467260B2
公开(公告)日：2008-12-16
申请号：US10961746
申请日：2004-10-08
申请人： Duane Arlyn Averill , John Michael Borkenhagen , Philip Rogers Hillier, III
发明人： Duane Arlyn Averill , John Michael Borkenhagen , Philip Rogers Hillier, III
IPC分类号： G06F12/00
CPC分类号： G06F12/0808 , G06F12/0804 , G06F12/126
摘要： An apparatus and method is disclosed for flushing a cache in a computing system. In a multinode computing system a cache in a first node may contain modified data in an address space of a second node. The cache in the first node must be purged prior to shutting down the first node. The computing system uses a random class replacement scheme for the cache. A cache flush routine sets a cache flush mode in a class replace select mechanism, overriding the random class replacement scheme. With the random class replacement scheme overridden, a minimum number of fetches will flush all the cache lines in the cache, each fetch loading the cache with a cache line not already in the cache. No additional delay penalty is incurred in a critical path through which fetches and stores to the cache must pass.
摘要翻译：公开了一种用于在计算系统中刷新高速缓存的装置和方法。在多节点计算系统中，第一节点中的高速缓存可以包含第二节点的地址空间中的修改数据。必须在关闭第一个节点之前清除第一个节点中的缓存。计算系统对缓存使用随机类替换方案。缓存刷新例程在类替换选择机制中设置缓存刷新模式，覆盖随机类替换方案。随着随机类替换方案被覆盖，最小数量的提取将刷新缓存中的所有高速缓存行，每次使用尚未在高速缓存中的缓存行来提取缓存。在缓存提取和存储必须通过的关键路径中不会产生额外的延迟损失。

19. 发明申请

US20080201495A1 HANDLING DMA OPERATIONS DURING A PAGE COPY 有权
标题翻译：在页面复制中处理DMA操作
公开(公告)号：US20080201495A1
公开(公告)日：2008-08-21
申请号：US12112932
申请日：2008-04-30
申请人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
发明人： Gerald Keith Bartley , John Michael Borkenhagen , William Paul Hovis , Daniel Paul Kolz
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that indicates the location currently being copied. If the page index of the DMA operation is less than the copy address pointer, the portion of the page that would be written to by the DMA operation has already been copied, so the DMA operation is performed to the physical address of the new page. If the page index of the DMA operation is greater than the copy address pointer, the portion of the page that would be written to by the DMA operation has not yet been copied, so the DMA operation is performed to the physical address of the old page.
摘要翻译：存储器控制器提供页面复制逻辑，以便在由存储器控制器复制页面期间在页面的DMA操作发生时确保数据一致性。页面复制逻辑将DMA操作的页面索引与指示当前正在复制的位置的复制地址指针进行比较。如果DMA操作的页面索引小于复制地址指针，则DMA操作将被写入的页面部分已被复制，因此DMA操作被执行到新页面的物理地址。如果DMA操作的页面索引大于复制地址指针，则DMA操作将被写入的页面部分尚未被复制，因此DMA操作被执行到旧页面的物理地址。

20. 发明授权

US07392445B2 Autonomic bus reconfiguration for fault conditions 失效
标题翻译：自动总线重新配置故障条件
公开(公告)号：US07392445B2
公开(公告)日：2008-06-24
申请号：US10660217
申请日：2003-09-11
申请人： John Michael Borkenhagen , Laura Marie Zumbrunnen
发明人： John Michael Borkenhagen , Laura Marie Zumbrunnen
IPC分类号： G01R31/28
CPC分类号： G06F11/2005
摘要： Methods and apparatus are provided that allow an electronic system having a signaling bus with a fault on a signaling conductor to operate at a degraded performance. A block of data is transferred from a first electronic unit to a second electronic unit over the signaling bus. A transmission sequence sends the block of data using all of the nonfaulty signaling conductors using a minimum number of beats required to complete the transmission.
摘要翻译：提供了允许具有在信令导体上具有故障的信令总线的电子系统以降级的性能来操作的方法和装置。数据块通过信令总线从第一电子单元传送到第二电子单元。传输序列使用所有非故障信令导体使用完成传输所需的最小次数发送数据块。

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