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11. 发明授权

US5694574A Method and apparatus for performing load operations in a computer system 失效
标题翻译：用于在计算机系统中执行加载操作的方法和装置
公开(公告)号：US5694574A
公开(公告)日：1997-12-02
申请号：US769860
申请日：1996-12-19
申请人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3834 , G06F12/0859 , G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for dispatching load operations in a computer system. The present invention includes a method and apparatus for determining when the load operation is ready for dispatched to memory. The load operation is then scheduled to dispatch from memory and then dispatched to memory. In the present invention, a load is determined ready when it is no longer blocked, such that there is no condition which produces a resource or address dependency causing the load to be blocked.
摘要翻译：一种用于在计算机系统中调度加载操作的方法和装置。本发明包括一种用于确定何时装载操作准备好发送到存储器的方法和装置。然后将加载操作调度为从内存分派，然后分派到内存。在本发明中，当不再阻塞负载时就准备就绪，使得不存在导致负载被阻塞的资源或地址依赖性的条件。

12. 发明授权

US06378062B1 Method and apparatus for performing a store operation 失效
标题翻译：用于执行存储操作的方法和装置
公开(公告)号：US06378062B1
公开(公告)日：2002-04-23
申请号：US08825427
申请日：1997-03-28
申请人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F930
CPC分类号： G06F9/3855 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： The present invention provides for executing store instructions with a processor. The present invention executes each of the store instructions by producing the data that is to be stored and by calculating the destination address to which the data is to be stored. In the present invention, the store instructions are executed to produce the destination address of the store instruction earlier than the prior art.
摘要翻译：本发明提供用处理器执行存储指令。本发明通过产生要存储的数据并通过计算要存储数据的目的地地址来执行每个存储指令。在本发明中，执行存储指令以比现有技术更早地产生存储指令的目的地地址。

13. 发明授权

US5881262A Method and apparatus for blocking execution of and storing load operations during their execution 失效
标题翻译：用于在其执行期间阻止执行和存储加载操作的方法和装置
公开(公告)号：US5881262A
公开(公告)日：1999-03-09
申请号：US928924
申请日：1997-09-12
申请人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F9/312 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3017 , G06F9/30043 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3842
摘要： A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and another memory operation currently pending in the system. When the dependency no longer exists, the present invention redispatches the load operation so that it completes.
摘要翻译：一种用于在计算机系统中执行加载操作的方法和装置。本发明包括一种用于调度要执行的加载操作的方法和装置。本发明在加载操作和系统中当前待处理的另一个存储器操作之间存在依赖关系时，停止加载操作的执行。当依赖关系不再存在时，本发明重新分派加载操作使其完成。

14. 发明授权

US5826109A Method and apparatus for performing multiple load operations to the same memory location in a computer system 失效
标题翻译：用于对计算机系统中的相同存储器位置执行多个加载操作的方法和装置
公开(公告)号：US5826109A
公开(公告)日：1998-10-20
申请号：US747197
申请日：1996-11-12
申请人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth , Robert W. Martell
发明人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , David B. Papworth , Robert W. Martell
IPC分类号： G06F9/38 , G06F12/08 , G06F13/18
CPC分类号： G06F12/0859 , G06F9/3824 , G06F9/3834
摘要： The present invention provides for executing load instructions with a processor having a non-blocking cache memory, wherein individual load operations are dispatched to the cache memory and the cache memory signals the prevent the load operation from being sent to external memory when the load operation misses the cache memory and there is already a currently pending bus cycle to the same cache line. This helps reduce bus traffic on the external bus.
摘要翻译：本发明提供用具有非阻塞高速缓冲存储器的处理器执行加载指令，其中单独的加载操作被分派到高速缓冲存储器，并且高速缓冲存储器发出信号，以防止当加载操作错过时将加载操作发送到外部存储器高速缓存存储器并且已经存在当前待处理的总线周期到同一高速缓存行。这有助于减少外部总线上的总线流量。

15. 发明授权

US5724536A Method and apparatus for blocking execution of and storing load operations during their execution 失效
公开(公告)号：US5724536A
公开(公告)日：1998-03-03
申请号：US177164
申请日：1994-01-04
申请人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F9/312 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3017 , G06F9/30043 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3842
摘要： A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and another memory operation currently pending in the system. When the dependency no longer exists, the present invention redispatches the load operation so that it completes.

16. 发明授权

US5420991A Apparatus and method for maintaining processing consistency in a computer system having multiple processors 失效
标题翻译：用于在具有多个处理器的计算机系统中维持处理一致性的装置和方法
公开(公告)号：US5420991A
公开(公告)日：1995-05-30
申请号：US177239
申请日：1994-01-04
申请人： Kris G. Konigsfeld , Jeffrey M. Abramson , Haitham Akkary , Glenn J. Hinton , Andrew F. Glew
发明人： Kris G. Konigsfeld , Jeffrey M. Abramson , Haitham Akkary , Glenn J. Hinton , Andrew F. Glew
IPC分类号： G06F9/312 , G06F9/38 , G06F12/08 , G06F9/46
CPC分类号： G06F9/30043 , G06F12/0831 , G06F9/3834
摘要： An apparatus for maintaining processor ordering in a multi-processor computer system wherein loads are performed speculatively. Speculative loads of each processor are temporarily stored in their respective processors' load buffer. When one of the processors performs a store, a snoop operation is performed on the other processors' load buffers. If the snoop results in a hit, a determination is made as to whether that load buffer contains any prior conflicting speculative loads which have been completed. If the load buffer does contain a prior conflicting load, a processor ordering violation signal is generated. In response to this signal, the violating load and all subsequent operations are canceled and re-executed at a later time.
摘要翻译：一种用于在多处理器计算机系统中维持处理器排序的装置，其中负载被推测地执行。每个处理器的推测负载临时存储在它们各自的处理器的负载缓冲器中。当其中一个处理器执行存储时，对其他处理器的负载缓冲区执行窥探操作。如果窥探导致命中，则确定该加载缓冲器是否包含已经完成的任何先前冲突的推测负载。如果加载缓冲区确实包含先前存在冲突的负载，则会生成处理器排序违规信号。响应于该信号，违反负载和所有后续操作将在以后被取消并重新执行。

17. 发明授权

US5708843A Method and apparatus for handling code segment violations in a computer system 失效
标题翻译：在计算机系统中处理代码段违规的方法和装置
公开(公告)号：US5708843A
公开(公告)日：1998-01-13
申请号：US544558
申请日：1995-10-18
申请人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Rohit Vidwans
发明人： Jeffrey M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Rohit Vidwans
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3865
摘要： A memory operation is issued in a processor. Upon detecting both that the memory operation produces a code segment violation and that the memory operation is blocked at retirement, a blocking signal is produced to block a bus access responsive to the memory operation. A second signal signifies that the memory operation completed.
摘要翻译：在处理器中发出存储器操作。在检测到存储器操作产生代码段违反并且在退出时存储器操作被阻止的情况下，产生阻塞信号以阻止响应于存储器操作的总线访问。第二个信号表示内存操作完成。

18. 发明授权

US5751983A Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations 失效
标题翻译：具有处理推测性调度负载操作的内存子系统的乱序处理器
公开(公告)号：US5751983A
公开(公告)日：1998-05-12
申请号：US538594
申请日：1995-10-03
申请人： Jeffrey M. Abramson , David B. Papworth , Haitham H. Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffrey M. Abramson , David B. Papworth , Haitham H. Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F9/38 , G06F3/38
CPC分类号： G06F9/3834
摘要： A method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by dispatching them to respective LOAD and STORE buffers in the memory subsystem. When a LOAD is subsequently dispatched for execution, the store buffer is searched for STOREs having unknown addresses. If any STOREs are found which are older than the dispatched LOAD, and which have an unknown address, the LOAD is tagged with an unknown STORE address identification (USAID). When a STORE is dispatched for execution, the LOAD buffer is searched for loads that have been denoted as mis-speculated loads. Mis-speculated loads are prevented from corrupting the architectural state of the machine with invalid data.
摘要翻译：用于在计算机系统中推测调度和/或执行LOAD的方法和装置包括无序处理器的存储器子系统，其通过将它们分派到存储器子系统中的相应LOAD和STORE缓冲器来处理LOAD和STORE操作。当随后调度LOAD进行执行时，搜索具有未知地址的STORE的存储缓冲区。如果发现任何比发送的LOAD更旧的存储区，并且具有未知地址，则LOAD被标记为未知的存储地址标识（USAID）。当调度STORE执行时，LOAD缓冲区将搜索已被表示为误推测负载的负载。可以防止误导的负载破坏机器的无效数据的架构状态。

19. 发明授权

US5526510A Method and apparatus for implementing a single clock cycle line replacement in a data cache unit 失效
标题翻译：用于在数据高速缓存单元中实现单个时钟周期线替换的方法和装置
公开(公告)号：US5526510A
公开(公告)日：1996-06-11
申请号：US315889
申请日：1994-09-30
申请人： Haitham Akkary , Mandar S. Joshi , Rob Murray , Brent E. Lince , Paul D. Madland , Andrew F. Glew , Glenn J. Hinton
发明人： Haitham Akkary , Mandar S. Joshi , Rob Murray , Brent E. Lince , Paul D. Madland , Andrew F. Glew , Glenn J. Hinton
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0859
摘要： The data cache unit includes a separate fill buffer and a separate write-back buffer. The fill buffer stores one or more cache lines for transference into data cache banks of the data cache unit. The write-back buffer stores a single cache line evicted from the data cache banks prior to write-back to main memory. Circuitry is provided for transferring a cache line from the fill buffer into the data cache banks while simultaneously transferring a victim cache line from the data cache banks into the write-back buffer. Such allows the overall replace operation to be performed in only a single clock cycle. In a particular implementation, the data cache unit is employed within a microprocessor capable of speculative and out-of-order processing of memory instructions. Moreover, the microprocessor is incorporated within a multiprocessor computer system wherein each microprocessor is capable of snooping the cache lines of data cache units of each other microprocessor. The data cache unit is also a non-blocking cache.
摘要翻译：数据高速缓存单元包括单独的填充缓冲器和单独的回写缓冲器。填充缓冲器存储用于转移到数据高速缓存单元的数据高速缓存组中的一个或多个高速缓存行。回写缓冲器在回写到主存储器之前存储从数据高速缓冲存储器中逐出的单个高速缓存行。提供电路用于将高速缓存行从填充缓冲器传送到数据高速缓存组，同时将受害缓存行从数据高速缓冲存储体传输到回写缓冲器。这样允许整个替换操作仅在单个时钟周期中执行。在特定实现中，在能够对存储器指令进行推测和无序处理的微处理器中采用数据高速缓存单元。此外，微处理器并入多处理器计算机系统中，其中每个微处理器能够窥探每个其他微处理器的数据高速缓存单元的高速缓存行。数据高速缓存单元也是非阻塞缓存。

20. 发明授权

US5564111A Method and apparatus for implementing a non-blocking translation lookaside buffer 失效
标题翻译：用于实现非阻塞转换后备缓冲器的方法和装置
公开(公告)号：US5564111A
公开(公告)日：1996-10-08
申请号：US315833
申请日：1994-09-30
申请人： Andrew F. Glew , Haitham Akkary , Robert P. Colwell , Glenn J. Hinton , David B. Papworth , Michael A. Fetterman
发明人： Andrew F. Glew , Haitham Akkary , Robert P. Colwell , Glenn J. Hinton , David B. Papworth , Michael A. Fetterman
IPC分类号： G06F9/38 , G06F11/00 , G06F12/10 , G06F11/34
CPC分类号： G06F9/3865 , G06F11/0751 , G06F12/1027 , G06F9/3842 , G06F2212/684
摘要： A non-blocking translation lookaside buffer is described for use in a microprocessor capable of processing speculative and out-of-order instructions. Upon the detection of a fault, either during a translation lookaside buffer hit or a page table walk performed in response to a translation lookaside buffer miss, information associated with the faulting instruction is stored within a fault register within the translation lookaside buffer. The stored information includes the linear address of the instruction and information identifying the age of instruction. In addition to storing the information within the fault register, a portion of the information is transmitted to a reordering buffer of the microprocessor for storage therein pending retirement of the faulting instruction. Prior to retirement of the faulting instruction, the translation lookaside buffer continues to process further instructions. Upon retirement of each instruction, the reordering buffer determines whether a fault had been detected for that instruction and, if so, the microprocessor is flushed. Then, a branch is taken into microcode. The microcode accesses the linear address and other information stored within the fault register of the translation lookaside buffer and handles the fault. The system is flushed and the microcode is executed only for faulting instructions which actually retire. As such, faults detected while processing speculative instructions based upon mispredicted branches do not prevent further address translations and do not cause the system to be flushed. Method and apparatus implementations are described herein.
摘要翻译：描述了用于能够处理推测和乱序指令的微处理器中的非阻塞转换后备缓冲器。在检测到故障时，无论是在翻译后备缓冲器命中还是响应于翻译后备缓冲器未命中执行的页表行走期间，与故障指令相关联的信息都存储在翻译后备缓冲器内的故障寄存器内。所存储的信息包括指令的线性地址和识别指令年龄的信息。除了将信息存储在故障寄存器之外，信息的一部分被发送到微处理器的重排序缓冲器以便存储在故障指令中。在故障指令退出之前，翻译后备缓冲区继续处理进一步的指令。在每个指令退出后，重新排序缓冲器确定是否检测到该指令发生故障，如果是，则清除微处理器。然后，一个分支被带入微码。微代码访问存储在翻译后备缓冲区的故障寄存器内的线性地址和其他信息，并处理故障。系统被刷新，微代码仅对实际退出的故障指令执行。因此，基于错误预测的分支处理推测性指令时检测到的故障不会妨碍进一步的地址转换，并且不会导致系统被刷新。本文描述了方法和装置实现。

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