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11. 发明申请

US20130036395A1 EFFICIENT SLACK PROJECTION FOR TRUNCATED DISTRIBUTIONS 失效
标题翻译：截断分布的有效插值投影
公开(公告)号：US20130036395A1
公开(公告)日：2013-02-07
申请号：US13197320
申请日：2011-08-03
申请人： Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
发明人： Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset.
摘要翻译：本发明的方面提供了用于在集成电路中突出松弛的解决方案。计算统计静态时序分析（SSTA）以在集成电路中的多个变化源上获得一组高斯分布。基于高斯分布，识别高斯分布的截断子集和余数子集。然后获得表示余数子集和截断子集之间的比率的数据因子。这些数据因子被应用于SSTA到根平方（RSS）项目，考虑到缺少截断子集的集成电路的松弛。

12. 发明申请

US20130018617A1 INTEGRATING MANUFACTURING FEEDBACK INTO INTEGRATED CIRCUIT STRUCTURE DESIGN 有权
标题翻译：集成制造反馈到集成电路结构设计
公开(公告)号：US20130018617A1
公开(公告)日：2013-01-17
申请号：US13182108
申请日：2011-07-13
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
IPC分类号： G06F19/00
CPC分类号： G06F17/5036 , G06F2217/84
摘要： Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.
摘要翻译：公开了将制造反馈集成到集成电路设计中的解决方案。在一个实施例中，公开了一种计算机实现的方法，包括：为第一集成电路产品定义可接受的收益率要求; 获取关于第一集成电路产品的制造数据; 对表示第一集成电路产品中的路径的数据执行回归分析，以基于可接受的产量要求和制造数据来定义多个参数设置; 确定与参数设置相关联的投影角以满足可接受的产量要求; 以及基于投影角和多个参数设置来修改第二集成电路产品的设计。

13. 发明授权

US08768679B2 System and method for efficient modeling of NPskew effects on static timing tests 有权
标题翻译：对静态时序测试的NPskew效应进行有效建模的系统和方法
公开(公告)号：US08768679B2
公开(公告)日：2014-07-01
申请号：US12894286
申请日：2010-09-30
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue X. Wang
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue X. Wang
IPC分类号： G06F17/50 , G06F7/60 , G06F13/10 , G06F11/26
CPC分类号： G06F13/105 , G06F11/261 , G06F17/50 , G06F17/5036
摘要： A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.
摘要翻译：使用摆动扰动模拟组合NFET（负场效应晶体管）/ PFET（正场效应晶体管）/ PFET（正场效应晶体管））半导体器件的NPskew效应的计算机实现的方法包括通过以下方式执行计算设备的定时测试：（1）评估干扰压摆在组合半导体器件上以强N /弱P方向进行定时测试结果; （2）组合半导体器件的评估扰动在弱N /强P方向上的时序测试结果; 和（3）在组合半导体器件上对平衡状态下的非扰动压摆进行定时测试结果。在执行每个测试之后，确定扰动和未扰动的压摆的哪个评估对组合半导体器件产生最保守的定时测试结果。基于确定最保守的定时测试结果，最终输出NPskew效果调整的定时测试结果。

14. 发明授权

US08458632B2 Efficient slack projection for truncated distributions 失效
标题翻译：用于截断分布的有效松弛投影
公开(公告)号：US08458632B2
公开(公告)日：2013-06-04
申请号：US13197320
申请日：2011-08-03
申请人： Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimer Zolotov
发明人： Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimer Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset.
摘要翻译：本发明的方面提供了用于在集成电路中突出松弛的解决方案。计算统计静态时序分析（SSTA）以在集成电路中的多个变化源上获得一组高斯分布。基于高斯分布，识别高斯分布的截断子集和余数子集。然后获得表示余数子集和截断子集之间的比率的数据因子。这些数据因子被应用于SSTA到根平方（RSS）项目，考虑到缺少截断子集的集成电路的松弛。

15. 发明申请

US20110055793A1 TIMING CLOSURE ON MULTIPLE SELECTIVE CORNERS IN A SINGLE STATISTICAL TIMING RUN 有权
标题翻译：在单个统计时序运行中多个选择角的定时关闭
公开(公告)号：US20110055793A1
公开(公告)日：2011-03-03
申请号：US12549061
申请日：2009-08-27
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Susan K. Lichtensteiger , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Susan K. Lichtensteiger , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks.
摘要翻译：描述了在单个统计时序运行中覆盖多个选择性定时角的方法。在一个实施例中，在涵盖无限制过程参数/环境条件的完整参数空间上运行单个统计时序分析。统计时间分析的结果预计为所选角。在具有最差松弛度的角落上进行定时关闭。

16. 发明申请

US20120084066A1 SYSTEM AND METHOD FOR EFFICIENT MODELING OF NPSKEW EFFECTS ON STATIC TIMING TESTS 有权
标题翻译：用于有效建模静态时间测试的NPSKEW效应的系统和方法
公开(公告)号：US20120084066A1
公开(公告)日：2012-04-05
申请号：US12894286
申请日：2010-09-30
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue X. Wang
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue X. Wang
IPC分类号： G06F17/50
CPC分类号： G06F13/105 , G06F11/261 , G06F17/50 , G06F17/5036
摘要： A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.
摘要翻译：使用摆动扰动模拟组合NFET（负场效应晶体管）/ PFET（正场效应晶体管）/ PFET（正场效应晶体管））半导体器件的NPskew效应的计算机实现的方法包括通过以下方式执行计算设备的定时测试：（1）评估干扰压摆在组合半导体器件上以强N /弱P方向进行定时测试结果; （2）组合半导体器件的评估扰动在弱N /强P方向上的时序测试结果; 和（3）在组合半导体器件上对平衡状态下的非扰动压摆进行定时测试结果。在执行每个测试之后，确定扰动和未扰动的压摆的哪个评估对组合半导体器件产生最保守的定时测试结果。基于确定最保守的定时测试结果，最终输出NPskew效果调整的定时测试结果。

17. 发明授权

US08141012B2 Timing closure on multiple selective corners in a single statistical timing run 有权
标题翻译：在单个统计计时运行中，在多个选择性角落定时关闭
公开(公告)号：US08141012B2
公开(公告)日：2012-03-20
申请号：US12549061
申请日：2009-08-27
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Susan K. Lichtensteiger , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Susan K. Lichtensteiger , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks.
摘要翻译：描述了在单个统计时序运行中覆盖多个选择性定时角的方法。在一个实施例中，在涵盖无限制过程参数/环境条件的完整参数空间上运行单个统计时序分析。统计时间分析的结果预计为所选角。在具有最差松弛度的角落上进行定时关闭。

18. 发明授权

US08104005B2 Method and apparatus for efficient incremental statistical timing analysis and optimization 有权
标题翻译：用于高效增量统计时序分析和优化的方法和装置
公开(公告)号：US08104005B2
公开(公告)日：2012-01-24
申请号：US12244512
申请日：2008-10-02
申请人： Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed.
摘要翻译：在一个实施例中，本发明是一种用于有效增量统计时序分析和优化的方法和装置。给定对n个随机变量中的至少一个的改变的用于确定n个随机变量的增量极值的方法的一个实施例包括获得n个随机变量，获得n个随机变量的第一极值，其中第一极值是在对所述n个随机变量中的至少一个随机变量进行改变之前计算的极值，去除所述n个随机变量中的所述至少一个以形成（n-1）子集，计算所述（n-1）子集的第二极值根据第一极值和n个随机变量中的至少一个，并且基于第（n-1）个子集的极值和n个随机变量中的至少一个来递增地输出n个随机变量的新的极值改变了。

19. 发明申请

US20120047477A1 Method of Measuring the Impact of Clock Skew on Slack During a Statistical Static Timing Analysis 有权
标题翻译：在统计静态时序分析中测量时钟偏移对松弛影响的方法
公开(公告)号：US20120047477A1
公开(公告)日：2012-02-23
申请号：US12857591
申请日：2010-08-17
申请人： Kerim Kalafala , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Kerim Kalafala , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof.
摘要翻译：计算时钟偏差对统计松弛的影响，存在统计上可变的时序量，这些时间量占时钟树共同部分的公共路径信誉，以及时钟树非共同的RSS信用。时钟偏移在每个发射和捕获路径对的基础上测量，作为后CPPR路径特定松弛（包括RSS信用），锁存到锁存延迟的总平均值，随机锁存的RSS值的函数到锁定延迟，测试保护时间和测试调整。该方法包括：执行初始的基于块的SSTA，包括CPPR分析; 选择至少一个启动和捕获路径对进行偏差分析; 对于至少一个路径对，记录后CPPR松弛，锁存到锁存延迟的总平均值，锁存器的RSS值到锁存延迟，测试保护时间和测试调整; 并量化时钟偏移对其统计松弛的影响。

20. 发明授权

US07212946B1 Method, system, and program product for accommodating spatially-correlated variation in a process parameter 失效
标题翻译：用于在过程参数中适应空间相关变化的方法，系统和程序产品
公开(公告)号：US07212946B1
公开(公告)日：2007-05-01
申请号：US11272234
申请日：2005-11-10
申请人： Natesan Venkateswaran , Chandramouli Visweswariah , Lizheng Zhang , Vladimir Zolotov
发明人： Natesan Venkateswaran , Chandramouli Visweswariah , Lizheng Zhang , Vladimir Zolotov
IPC分类号： G06F17/18 , G06F15/00 , G06F19/00
CPC分类号： G06F17/5031
摘要： The invention provides a method, system, and program product for accommodating spatially-correlated variation in a process parameter during statistical timing of a circuit. In one embodiment, the method includes dividing an area of the circuit into a plurality of grid cells; associating an independent random variable with each of the plurality of grid cells; and expressing at least one spatially-correlated parameter of a first grid cell as a function of the random variables associated with the first grid cell and at least one neighboring grid cell.
摘要翻译：本发明提供一种用于在电路的统计定时期间适应处理参数的空间相关变化的方法，系统和程序产品。在一个实施例中，该方法包括将电路的区域划分成多个网格单元; 将独立随机变量与所述多个网格单元中的每一个相关联; 以及将与第一网格单元和至少一个相邻网格单元相关联的随机变量的函数表达为第一网格单元的至少一个空间相关参数。

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