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11. 发明授权

US07398488B2 Trace equivalence identification through structural isomorphism detection with on the fly logic writing 有权
标题翻译：通过结构同构检测跟踪逻辑写作的跟踪等价识别
公开(公告)号：US07398488B2
公开(公告)日：2008-07-08
申请号：US11383770
申请日：2006-05-17
申请人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing trace equivalent identification by structural isomorphism detection, the method comprising: synthesizing a first netlist into a second netlist, the second netlist including two-input AND gates, inversions, inputs, constants, and registers; constructing a third netlist, the third netlist being a pseudo-canonical netlist that uses calls to algorithms for constructing a netlist for gate g1 and for constructing a netlist for gate g2, where g1 and g2 are gates; and performing an isomorphism check of gates g1 and g2.
摘要翻译：一种用于通过结构同构检测来执行跟踪等价识别的方法，所述方法包括：将第一网表合成到第二网表中，所述第二网表包括双输入与门，反转，输入，常数和寄存器; 构造第三网表，第三网表是伪规范网表，其使用对算法的调用来构造门g 1的网表，并且用于构造门g 2的网表，其中g 1和g 2是门; 并执行门g 1和g 2的同构检查。

12. 发明申请

US20080134113A1 Method and System for Enhanced Verification by Closely Coupling a Structural Overapproximation Algorithm and a Structural Satisfiability Solver 失效
标题翻译：通过紧密耦合结构过近似算法和结构满意度求解器来增强验证的方法和系统
公开(公告)号：US20080134113A1
公开(公告)日：2008-06-05
申请号：US12013163
申请日：2008-01-11
申请人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for performing verification are disclosed. A first abstraction of an initial design netlist containing a first target is created and designated as a current abstraction, and the current abstraction is unfolded by a selectable depth. A composite target is verified using a satisfiability solver, and in response to determining that the verifying step has hit the composite target, a counterexample to is examined to identify one or more reasons for the first target to be asserted. One or more refinement pairs are built by examining the counterexample, and a second abstraction is built by composing the refinement pairs. One or more learned clauses and one or more invariants to the second abstraction and the second abstraction is chosen as the current abstraction. The current abstraction is verified with the satisfiability solver.
摘要翻译：公开了一种用于执行验证的方法，系统和计算机程序产品。创建包含第一个目标的初始设计网表的第一个抽象，并将其指定为当前抽象，并且当前抽象由可选深度展开。使用可满足性求解器验证复合目标，并且响应于确定验证步骤已经击中复合目标，检查反例以识别要被断言的第一目标的一个或多个原因。通过检查反例来构建一个或多个细化对，并通过组合细化对构建第二个抽象。选择一个或多个学习子句和一个或多个第二抽象和第二抽象的不变量作为当前抽象。目前的抽象是用可满足性求解器来验证的。

13. 发明授权

US08185852B2 Performing minimization of input count during structural netlist overapproximation 失效
标题翻译：在结构化网表过度近似期间执行输入计数的最小化
公开(公告)号：US08185852B2
公开(公告)日：2012-05-22
申请号：US12047361
申请日：2008-03-13
申请人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification is disclosed. The method includes selecting a set of gates to add to a first localization netlist and forming a refinement netlist. A min-cut is computed with sinks having one or more gates in the refinement netlist and sources comprising one or more inputs of an original netlist and one or more registers registers of the original netlist which are not part of the refinement netlist. A final localized netlist is obtained by adding one or more gates to the refinement netlist to grow the refinement netlist until reaching one or more cut-gates of the min-cut.
摘要翻译：公开了一种用于执行验证的方法。该方法包括选择一组门以添加到第一定位网表并形成细化网表。使用在细化网表中具有一个或多个门的信宿和包括原始网表的一个或多个输入和不属于细化网表的原始网表的一个或多个寄存器寄存器的源来计算最小值。通过将一个或多个门添加到细化网表来获得最终的本地化网表，以增加细化网表，直到达到最小切割的一个或多个切割点。

14. 发明授权

US08042075B2 Method, system and application for sequential cofactor-based analysis of netlists 有权
标题翻译：网表的顺序辅因子分析的方法，系统和应用
公开(公告)号：US08042075B2
公开(公告)日：2011-10-18
申请号：US12410962
申请日：2009-03-25
申请人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F9/45 , G06F9/455 , G06F17/50
CPC分类号： G06F17/5022
摘要： Methods, systems and computer products are provided for reducing the design size of an integrated circuit while preserving the behavior of the design with respect to verification results. A multiplexer is inserted at the gate being analyzed, and the multiplexer selector is controlled to provide a predetermined output for one frame at the point being analyzed. It is then determined whether the circuit remains equivalent during application of the predetermined output in order to decide whether the gate being analyzed is a candidate for replacement.
摘要翻译：提供了方法，系统和计算机产品，用于减少集成电路的设计尺寸，同时保持设计相对于验证结果的行为。在被分析的门处插入复用器，并且多路复用器选择器被控制以在被分析的点处为一帧提供预定的输出。然后在应用预定输出期间确定电路是否保持等效，以便确定被分析的门是否是替换候选。

15. 发明授权

US07788616B2 Method and system for performing heuristic constraint simplification 失效
公开(公告)号：US07788616B2
公开(公告)日：2010-08-31
申请号：US11940755
申请日：2007-11-15
申请人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparamaterization to simplify the first computer-design constraint. In response to determining that the first computer-design constraint is not eliminated, the first computer-design constraint is set equal to a dead-end state of the constraint. A structural preimage of the first computer-design constraint is created, in response to determining that a combination of a target and the dead-end state of the first computer-design constraint is equal to a combination of the target and the structural preimage of the first computer-design constraint, the first computer-design constraint is set equal to the structural preimage.

16. 发明授权

US07734452B2 Method and system for performing ternary verification 有权
标题翻译：执行三元验证的方法和系统
公开(公告)号：US07734452B2
公开(公告)日：2010-06-08
申请号：US11675698
申请日：2007-02-16
申请人： Jason R. Baumgartner , Hari Mony , Viresh Paruthi , Matyas A. Sustik
发明人： Jason R. Baumgartner , Hari Mony , Viresh Paruthi , Matyas A. Sustik
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings.
摘要翻译：公开了一种用于执行三元验证的方法和系统。最初，从逻辑电路设计的二进制模型生成三元模型。然后记录用于对三元模型进行编码的配对。接下来，通过去除所有无效的门对配对来减少所记录的门对配对数。对具有减少数量的门对配对的三元模型进行三进制验证。

17. 发明授权

US07478344B2 Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms 失效
标题翻译：通过紧密耦合结构可满足性求解器和重写算法来增强验证的方法和系统
公开(公告)号：US07478344B2
公开(公告)日：2009-01-13
申请号：US11443906
申请日：2006-05-31
申请人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： A61F13/472 , A61F13/202 , A61F13/2051 , A61F13/206 , A61F13/2065 , A61F13/2068 , G06F8/72
摘要： A method, system and computer program product are disclosed. The method includes initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a rewriting module, a second variable to limit a time for satsifability solver operations with respect to said initial design by a staisfiability solver module and a third variable to limit a maximum number of rewrite iterations with respect to said initial design. A timer is called to track said rewrite time and a local logic rewriting operation is run on said initial design with said rewrite module. In response to determining that all of all targets for said initial design netlist are not solved, whether a rewrite time is expired is determined. In response to determining that said rewrite time is not expired, AND refactoring is run. In response to determining that said rewrite time is not expired, XOR refactoring is run.
摘要翻译：公开了一种方法，系统和计算机程序产品。该方法包括：初始化第一变量以限制由重写模块相对于初始设计的重写操作的重写时间;第二变量，用于限制由可靠性求解器模块相对于所述初始设计的可乘坐解算器操作的时间;以及第三变量以限制相对于所述初始设计的最大重写迭代次数。调用定时器以跟踪所述重写时间，并且利用所述重写模块在所述初始设计上运行本地逻辑重写操作。响应于确定所有初始设计网表的所有目标未被解决，确定重写时间是否到期。响应于确定所述重写时间未过期，并且运行重构。响应于确定所述重写时间未过期，运行XOR重构。

18. 发明申请

US20080229263A1 PERFORMING UTILIZATION OF TRACES FOR INCREMENTAL REFINEMENT IN COUPLING A STRUCTURAL OVERAPPROXIMATION ALGORITHM AND A SATISFIABILITY SOLVER 审中-公开
标题翻译：执行结构化过度预测算法和可靠性解算器的联合优化中的跟踪的实现
公开(公告)号：US20080229263A1
公开(公告)日：2008-09-18
申请号：US12130047
申请日：2008-05-30
申请人： JASON R. BAUMGARTNER , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
发明人： JASON R. BAUMGARTNER , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, system and computer program product for performing verification are disclosed. The method includes creating and designating as a current abstraction a first abstraction of an initial design netlist containing a first target and unfolding the current abstraction by a selectable depth. A composite target is verified, using a satisfiability solver and, in response to determining that the verifying step has hit the composite target, a counterexample is examined to identify one or more reasons for the first target to be asserted. One or more refinement pairs are built by examining the counterexample and a second abstraction is built by composing the refinement pairs. A new target is built over one or more cutpoints in the first abstraction that is asserted when the one or more cutpoints assume values in the counterexample, and the new target is verified with the satisfiability solver.
摘要翻译：公开了一种用于执行验证的方法，系统和计算机程序产品。该方法包括创建和指定作为当前抽象的包含第一目标的初始设计网表的第一抽象并且通过可选深度展开当前抽象。使用可满足性求解器来验证复合目标，并且响应于确定验证步骤已经达到复合目标，检查反例以识别要被断言的第一目标的一个或多个原因。通过检查反例来构建一个或多个细化对，通过组合细化对构建第二个抽象。当一个或多个切点在反例中假定值时，第一个抽象中的一个或多个切点建立一个新目标，并且使用可满足性求解器验证新目标。

19. 发明授权

US08473882B2 Method and system for scalable reduction in registers with SAT-based resubstitution 失效
标题翻译：用于基于SAT重新配置的寄存器的可缩减方法和系统
公开(公告)号：US08473882B2
公开(公告)日：2013-06-25
申请号：US13415924
申请日：2012-03-09
申请人： Jason R. Baumgartner , Michael L. Case , Hari Mony , Viresh Paruthi
发明人： Jason R. Baumgartner , Michael L. Case , Hari Mony , Viresh Paruthi
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505
摘要： A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated.
摘要翻译：在验证逻辑网络设计之前，用于减小逻辑网络设计大小的方法，系统和计算机程序产品。该方法包括消除寄存器以减小逻辑网络设计的大小; 从而增加验证过程的速度和功能，并减小逻辑网络设计的大小。系统识别所选择的寄存器的一个或多个兼容的重新配置，其中兼容重新配置将所选择的寄存器表示为一个或多个预先存在的固定初始状态的寄存器。利用设计不变量来改进重组。当再进行一次重新配置时，系统将删除所选择的寄存器以减小逻辑网络设计的大小。作为重新配置处理的结果，生成尺寸减小的逻辑网络设计。

20. 发明授权

US08122403B2 Trace containment detection of combinational designs via constraint-based uncorrelated equivalence checking 有权
标题翻译：通过基于约束的不相关等价检查的组合设计的跟踪容限检测
公开(公告)号：US08122403B2
公开(公告)日：2012-02-21
申请号：US12425095
申请日：2009-04-16
申请人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
发明人： Jason R. Baumgartner , Robert L. Kanzelman , Hari Mony , Viresh Paruthi
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504
摘要： Methods and systems are provided for producing more efficient digital circuitry designs by identifying trace-containment for a sequential circuitry design netlist through the use of constraint-based uncorrelated equivalence checking. A set of candidate input netlist sets n1 and n2 is first uncorrelated and then submitted for equivalence checking. Mismatches discovered during the equivalence checking are avoided by imposing constraint to the input set until discovering an equivalency relationship between the input sets n1 and n2.
摘要翻译：提供了方法和系统，用于通过使用基于约束的不相关等价检查来识别顺序电路设计网表的跟踪容纳来产生更有效的数字电路设计。一组候选输入网表集n1和n2首先不相关，然后提交用于等价检查。在等效检查期间发现的不匹配通过对输入集施加约束来避免，直到发现输入集n1和n2之间的等价关系。

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