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11. 发明授权

US07318222B2 Methods for execution control acquistion of a program and for executing an optimized version of a program 有权
标题翻译：用于执行控制获取程序和执行程序的优化版本的方法
公开(公告)号：US07318222B2
公开(公告)日：2008-01-08
申请号：US10650190
申请日：2003-08-27
申请人： Jan Civlin
发明人： Jan Civlin
IPC分类号： G06F9/45
CPC分类号： G06F9/45525 , G06F9/4812
摘要： In a method for execution control acquisition of a program, during the execution of the program, it is determined when a hardware performance counter has reached a threshold. When the threshold is reached, execution control is switched to a dynamic optimizer. Thereafter, an optimized version of the program is executed. In a method for executing an optimized version of a program, during execution of the optimized version, an interrupt is received and execution control is returned to an operating system. An original version of the program is then executed. During the execution of the original version, a hardware performance counter is monitored. When the hardware performance counter reaches a threshold during the execution of the original version, execution control is switched to a dynamic optimizer. Thereafter, the execution of the optimized version of the program is continued as directed by the dynamic optimizer.
摘要翻译：在程序的执行控制获取方法中，在程序执行期间，确定硬件性能计数器何时达到阈值。当达到阈值时，执行控制切换到动态优化器。此后，执行程序的优化版本。在执行程序的优化版本的方法中，在优化版本的执行期间，接收到中断并将执行控制返回到操作系统。然后执行程序的原始版本。在执行原始版本期间，监视硬件性能计数器。当硬件性能计数器在执行原始版本期间达到阈值时，执行控制切换到动态优化器。此后，根据动态优化器的指示继续执行程序的优化版本。

12. 发明申请

US20070294681A1 Systems and methods for profiling an application running on a parallel-processing computer system 有权
标题翻译：用于分析在并行处理计算机系统上运行的应用程序的系统和方法
公开(公告)号：US20070294681A1
公开(公告)日：2007-12-20
申请号：US11716508
申请日：2007-03-09
申请人： Nathan D. Tuck , Matthew N. Papakipos , Brian K. Grant , Christopher G. Demetriou , Jan Civlin
发明人： Nathan D. Tuck , Matthew N. Papakipos , Brian K. Grant , Christopher G. Demetriou , Jan Civlin
IPC分类号： G06F9/45
CPC分类号： G06F11/3466 , G06F11/3404 , G06F11/3476 , G06F11/3612 , G06F2201/865
摘要： A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of the parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. A profiling tool is used to collect, analyze, and visualize the performance data of an application in connection with its execution on a parallel-processing computer system through the runtime system. This profiling tool greatly enhances an application developer's ability to understand how an application is executed on the parallel-processing computer system and fine-tune the application to achieve high performance.
摘要翻译：根据本发明实现的运行时系统提供了一种用于并行处理计算机系统的应用平台。这样的运行时系统使得用户能够利用并行处理计算机系统的计算能力来加速/优化其应用程序中的数字和阵列密集型计算。分析工具用于收集，分析和可视化与通过运行时系统在并行处理计算机系统上执行相关的应用程序的性能数据。此分析工具大大提高了应用程序开发人员了解应用程序在并行处理计算机系统上的执行情况，并调整应用程序以实现高性能的能力。

13. 发明授权

US06968429B2 Method and apparatus for controlling line eviction in a cache 有权
标题翻译：用于控制缓存中线路驱逐的方法和装置
公开(公告)号：US06968429B2
公开(公告)日：2005-11-22
申请号：US10371790
申请日：2003-02-20
申请人： Jan Civlin
发明人： Jan Civlin
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0875 , G06F12/126
摘要： One embodiment of the present invention provides a system for controlling cache line eviction. The system operates by first receiving a sequence of instructions at a processor during execution of a program, wherein the sequence of instructions causes a cache line to be loaded into the cache. Next, the system examines the sequence of instructions to determine if an associated cache line includes only scratch data that will not be reused. If so, upon loading the cache line into the cache, the system marks the cache line as containing only scratch data, which allows the cache line to be evicted next from the cache.
摘要翻译：本发明的一个实施例提供了一种用于控制高速缓存行驱逐的系统。该系统通过在执行程序期间首先在处理器处接收指令序列来操作，其中指令序列使高速缓存行被加载到高速缓存中。接下来，系统检查指令序列以确定相关联的高速缓存行是否仅包括将不被重用的临时数据。如果是这样，在将高速缓存行加载到高速缓存中时，系统将高速缓存行标记为仅包含暂存数据，这允许高速缓存行从缓存中逐出。

14. 发明申请

US20050060694A1 Methods and hardware for safe memory allocation in arbitrary program environments 有权
标题翻译：在任意程序环境中安全内存分配的方法和硬件
公开(公告)号：US20050060694A1
公开(公告)日：2005-03-17
申请号：US10667274
申请日：2003-09-16
申请人： Jan Civlin
发明人： Jan Civlin
IPC分类号： G06F9/45
CPC分类号： G06F12/145 , G06F12/0223
摘要： In a method for dynamic allocation of memory address space, an original version of a program is executed. This execution includes the execution of a request to use memory address space occupied by an optimized version of the program that is protected from modification. When this request is detected, execution control is passed to an optimization code that was used to define the optimized program. The optimization code copies a portion of the optimized program residing in the memory address space requested by the original program, writes the copied portion to unallocated memory address space, and adjusts the code of the optimized program. The protection of the copied portion of the optimized program is released, and execution control is returned to the original program. The request to use the memory address space occupied by the portion of the optimized for which the protection has been released is then re-executed.
摘要翻译：在用于动态分配存储器地址空间的方法中，执行程序的原始版本。该执行包括执行使用被保护以免修改的程序的优化版本所占用的存储器地址空间的请求。当检测到此请求时，执行控制将传递给用于定义优化程序的优化代码。优化代码复制驻留在原始程序请求的存储器地址空间中的优化程序的一部分，将复制的部分写入未分配的存储器地址空间，并调整优化程序的代码。释放优化程序复制部分的保护，执行控制返回到原程序。然后重新执行使用被优化的部分所占用的存储器地址空间的请求，该部分被保护已被释放。

15. 发明授权

US06671196B2 Register stack in cache memory 有权
标题翻译：在缓存中注册堆栈
公开(公告)号：US06671196B2
公开(公告)日：2003-12-30
申请号：US10086911
申请日：2002-02-28
申请人： Jan Civlin
发明人： Jan Civlin
IPC分类号： G11C700
CPC分类号： G06F9/30138 , G06F9/30116 , G06F9/30134 , G06F12/0875
摘要： A CPU includes a register file including a plurality of architectural registers for storing data loaded from a primary memory for execution by the CPU. A stack cache memory coupled to the register file includes a plurality of cache lines, each of which corresponds to one of the architectural registers and implements a first-in, last-out queue for data spilled from the corresponding architectural register. Data spilled from the register file into the stack cache memory is maintained in the stack cache until subsequently restored to the register file without accessing primary memory. The stack cache memory does not participate in cache writeback operations to primary memory.
摘要翻译： CPU包括一个寄存器文件，该寄存器文件包括多个架构寄存器，用于存储从主存储器加载以供CPU执行的数据。耦合到寄存器文件的堆栈高速缓冲存储器包括多个高速缓存线，每条缓存线对应于架构寄存器中的一个，并且实现从相应架构寄存器溢出的数据的先入先出队列。从寄存器文件溢出到堆栈高速缓冲存储器中的数据保留在堆栈高速缓存中，直到随后恢复到寄存器文件而不访问主存储器。堆栈缓存内存不参与主内存的高速缓存回写操作。

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