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11. 发明申请

US20050144400A1 Hierarchical virtual model of a cache hierarchy in a multiprocessor system 有权
标题翻译：多处理器系统中缓存层次结构的分层虚拟模型
公开(公告)号：US20050144400A1
公开(公告)日：2005-06-30
申请号：US11069848
申请日：2005-02-28
申请人： Herbert Hum , James Goodman
发明人： Herbert Hum , James Goodman
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F12/0815 , G06F2212/2542
摘要： The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.
摘要翻译：本文描述的高速缓存一致性协议可用于维护系统的虚拟模型，其中虚拟模型不随系统配置改变而改变。一般来说，虚拟模型是基于系统中的每个节点可以直接与系统中的其他节点通信的假设。在一个实施例中，对于每个高速缓存行，高速缓存行的地址用于将节点指定为“家”节点，将所有其他节点指定为“对等”节点。该协议指定一组消息，用于与线路的家庭节点通信，另一组消息用于与线路的对等节点进行通信。

12. 发明授权

US07009419B2 Method and apparatus for selecting an encryption integrated circuit operating mode 有权
公开(公告)号：US07009419B2
公开(公告)日：2006-03-07
申请号：US10687165
申请日：2003-10-16
申请人： James Goodman
发明人： James Goodman
IPC分类号： H03K19/00 , H04L9/00
CPC分类号： G06F21/74 , G01R31/31704 , G01R31/31719 , G01R31/318558 , G01R31/318588
摘要： A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initialising it.

13. 发明申请

US20050091944A1 Flaps closer apparatus 有权
标题翻译：打开更近的装置
公开(公告)号：US20050091944A1
公开(公告)日：2005-05-05
申请号：US10976608
申请日：2004-10-29
申请人： James Goodman
发明人： James Goodman
IPC分类号： B31B50/48 , B65B7/20
CPC分类号： B65B7/20
摘要： A flaps closing apparatus for closing full flap boxes is provided. The apparatus includes a flaps closing assembly with a first brake mechanism and closing bars with a second brake mechanism. The first brake mechanism controls the vertical motion of the flaps closing assembly with respect to the flaps closing apparatus. The second brake mechanism holds the closing bars in an angled configuration and at a first predetermined vertical position permits the bars to pivot to a horizontal configuration. A flap sealing assembly includes a pair of compression plates positioned outside the flaps closing assembly. A compression plate actuating mechanism draws the compression plates inwardly to urge side flaps of the full flap box into contact with sides of the full flap box at a second predetermined vertical position. A vertical movement mechanism lowers and raises the apparatus.
摘要翻译：提供一种用于关闭整个皮瓣盒的折片关闭装置。该装置包括具有第一制动机构的挡板关闭组件和具有第二制动机构的关闭杆。第一制动机构控制翼片关闭组件相对于翼片关闭装置的垂直运动。第二制动机构将闭合杆保持成倾斜的构造，并且在第一预定垂直位置允许杆枢转到水平构型。翼片密封组件包括位于翼片关闭组件外侧的一对压板。压缩板致动机构向内拉动压板以促使完整挡板的侧翼在第二预定垂直位置处与完全挡板的侧面接触。垂直移动机构降低并升高装置。

14. 发明授权

US06466048B1 Method and apparatus for switchably selecting an integrated circuit operating mode 有权
标题翻译：用于切换选择集成电路工作模式的方法和装置
公开(公告)号：US06466048B1
公开(公告)日：2002-10-15
申请号：US09862339
申请日：2001-05-23
申请人： James Goodman
发明人： James Goodman
IPC分类号： H03K1900
CPC分类号： G06F21/74 , G01R31/31704 , G01R31/31719 , G01R31/318558 , G01R31/318588
摘要： A method and circuit for preventing external access to secure data of an integrated circuit while supporting DFT is disclosed. In accordance with the method the integrated circuit is automatically placed into the test mode at integrated circuit power-up from a power-down state. At power up, secure data is other than present within a secure data-path of the integrated circuit. Access is provided to the secure data path via a second data path coupled with the first secure data-path. Via the access path, data other than secure data is provided to the integrated circuit, the data for performing test functions of the integrated circuit operating in the test mode. Once data other than secure data is provided to first secure data path, the test mode is terminated and access via other than the secure ports is disabled. The test mode is only re-entered by powering down the integrated circuit and re-initializing it.
摘要翻译：公开了一种用于在支持DFT的同时防止外部访问集成电路的安全数据的方法和电路。根据该方法，集成电路在从掉电状态的集成电路上电时自动进入测试模式。在上电时，安全数据不同于存在于集成电路的安全数据路径内。经由与第一安全数据路径耦合的第二数据路径向安全数据路径提供访问。通过访问路径，除了安全数据之外的数据被提供给集成电路，用于执行在测试模式下操作的集成电路的测试功能的数据。一旦将安全数据以外的数据提供给第一安全数据路径，则终止测试模式，并且禁用除安全端口之外的访问。测试模式只能通过关闭集成电路并重新初始化来重新输入。

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