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11. 发明授权

US08347194B2 Hierarchical decoding apparatus 有权
标题翻译：分层解码装置
公开(公告)号：US08347194B2
公开(公告)日：2013-01-01
申请号：US12428511
申请日：2009-04-23
申请人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
发明人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
IPC分类号： G06F11/00
CPC分类号： H03M13/2906 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/1117 , H03M13/1194 , H03M13/136 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/296 , H03M13/3707 , H03M13/3738
摘要： A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.
摘要翻译：解码器包括多个解码器级和控制器。解码器级使用相应的不同解码算法对接收到的信号执行解码操作。控制器确定解码器中的一个相对于接收信号执行的解码操作是否成功，并且响应于确定的结果来控制每个其他解码器级的解码操作。

12. 发明申请

US20100251077A1 STORAGE DEVICE AND DATA STORAGE SYSTEM INCLUDING OF THE SAME 审中-公开
标题翻译：存储设备和包括其的数据存储系统
公开(公告)号：US20100251077A1
公开(公告)日：2010-09-30
申请号：US12729285
申请日：2010-03-23
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
IPC分类号： G06F12/02 , H03M13/05 , G06F11/10
CPC分类号： G06F11/1048
摘要： A storage device includes a controller unit and a memory cell array. The controller unit is for outputting data through a first data path or a second data path according to a property of externally supplied input data. The memory cell array includes a first memory and a second memory, and receives and stores the data from the controller unit output through the first and second data paths. The first memory has a different memory cell structure than the second memory.
摘要翻译：存储装置包括控制器单元和存储单元阵列。控制器单元用于根据外部提供的输入数据的属性通过第一数据路径或第二数据路径输出数据。存储单元阵列包括第一存储器和第二存储器，并且通过第一和第二数据路径接收并存储来自控制器单元输出的数据。第一存储器具有与第二存储器不同的存储单元结构。

13. 发明申请

US20090307566A1 ITERATIVE DECODING METHOD AND APPARATUS 有权
标题翻译：迭代解码方法和装置
公开(公告)号：US20090307566A1
公开(公告)日：2009-12-10
申请号：US12475640
申请日：2009-06-01
申请人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
发明人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/1105 , H03M13/136 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2906 , H03M13/3738 , H03M13/3753 , H04L1/0051 , H04L1/0057
摘要： An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.
摘要翻译：公开了一种迭代解码方法，并且包括相对于奇偶校验方程顺序执行多个迭代解码周期，直到奇偶校验方程被解析为止，或者在执行迭代次数期间达到迭代解码周期的最大数量N 解码周期，在数据缓冲器中存储对应于最小数量的位错误的一组可变节点的最小估计值，并且当迭代解码周期数达到时，输出存储在数据缓冲器中的最小估计值作为最终解码结果 N.

14. 发明申请

US20090287975A1 Memory device and method of managing memory data error 有权
标题翻译：内存设备和管理内存数据错误的方法
公开(公告)号：US20090287975A1
公开(公告)日：2009-11-19
申请号：US12453163
申请日：2009-04-30
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
IPC分类号： G06F11/10 , G11C16/04 , G11C16/06 , G11C16/02 , H03M13/03
CPC分类号： G11C16/10 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3454 , G11C29/00 , G11C2211/5621 , G11C2211/5634
摘要： Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.
摘要翻译：提供了存储器件和/或管理存储器数据错误的方法。存储器件检测并校正从多个存储器单元读取的数据的错误位，并且识别存储检测到的错误位的存储单元。存储装置向多个第一存储器单元中的每一个分配验证电压，对应于所识别的存储单元的校正位的分配的验证电压，对应于剩余存储单元的读取数据的分配验证电压。存储装置使用分配的验证电压重新调整存储在多个存储单元中的数据。由此，可以增加存储装置的数据的保持期。

15. 发明授权

US08656258B2 Method of encoding and decoding multi-bit level data 有权
标题翻译：多位电平数据的编码和解码方法
公开(公告)号：US08656258B2
公开(公告)日：2014-02-18
申请号：US12429718
申请日：2009-04-24
申请人： Yong June Kim , Jae Hong Kim , Kyoung Lae Cho , Jun Jin Kong , Ki Jun Lee , Ha Bong Chung , Keun Sung Choi
发明人： Yong June Kim , Jae Hong Kim , Kyoung Lae Cho , Jun Jin Kong , Ki Jun Lee , Ha Bong Chung , Keun Sung Choi
IPC分类号： G06F11/00
CPC分类号： H03M13/451 , G06F11/1072
摘要： A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P.
摘要翻译：一种编码多位电平数据的方法包括：根据传输符号确定产生的误差模式的范围，根据误差模式的范围来编码与发送符号对应的P位电平的M位电平，并且排除P位电平的PM位电平的编码。变量P是至少为2的值的自然数，变量M是小于P的自然数。

16. 发明授权

US08352808B2 Data storage system and device with randomizer/de-randomizer 有权
标题翻译：数据存储系统和具有随机化/去随机化器的设备
公开(公告)号：US08352808B2
公开(公告)日：2013-01-08
申请号：US12573246
申请日：2009-10-05
申请人： Yong June Kim , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho
发明人： Yong June Kim , Jun Jin Kong , Jae Hong Kim , Kyoung Lae Cho
IPC分类号： G06F11/00 , G06F12/00
CPC分类号： G06F11/1008
摘要： A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined characteristic, a randomizer configured to selectively randomize or not randomize the write data in response to the first control signal to thereby generate randomized write data, and a data storage unit configured to store the randomized write data.
摘要翻译：数据存储装置接收写入数据，并且包括控制器，被配置为确定写入数据的特性并响应于所确定的特性提供第一控制信号;随机化器，被配置为响应于第一个数据，选择性地随机化或不使写入数据随机化从而生成随机写入数据，以及数据存储单元，被配置为存储随机写入数据。

17. 发明申请

US20100020620A1 Memory device and method of programming thereof 有权
标题翻译：存储器件及其编程方法
公开(公告)号：US20100020620A1
公开(公告)日：2010-01-28
申请号：US12453964
申请日：2009-05-28
申请人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
发明人： Yong June Kim , Kyoung Lae Cho , Jae Hong Kim , Jun Jin Kong , Hong Rak Son
IPC分类号： G11C16/04 , G06F12/00
CPC分类号： G11C11/5628 , G11C7/1006
摘要： Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.
摘要翻译：示例性实施例可以提供存储器设备和存储器数据编程方法。根据示例性实施例的存储器件可编码第一数据页以产生至少一个第一码字，并对第二数据页进行编码以产生第二码字。存储器装置可以利用连续零个数的最大值和连续零数的第二最大值中的至少一个来生成第一码字。存储器件可以将至少一个第一代码字和至少一个第二代码字编程到多个多位单元。

18. 发明申请

US20090193313A1 Method and apparatus for decoding concatenated code 审中-公开
标题翻译：用于解码级联代码的方法和装置
公开(公告)号：US20090193313A1
公开(公告)日：2009-07-30
申请号：US12149999
申请日：2008-05-12
申请人： Jun Jin Kong , Jae Hong Kim , Yong June Kim , Young Hwan Lee
发明人： Jun Jin Kong , Jae Hong Kim , Yong June Kim , Young Hwan Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/29 , H03M13/1102 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/2906 , H03M13/2957 , H03M13/2975 , H03M13/3738 , H03M13/6561
摘要： Provided are apparatuses for decoding a concatenated code and methods for the same that may improve the decoding speed of a concatenated code based on a likelihood value with respect to output from a plurality of decoders.A method of decoding a concatenated code may include: calculating a likelihood value of concatenated encoded received data; performing first decoding for the received data based on the calculated likelihood value to generate first decoded data; performing second decoding for the first decoded data to generate second decoded data; and determining whether to perform iterative decoding based on the second decoded data.According to example embodiments, it is possible to directly manage the quality of concatenated decoded data to thereby accurately determine whether to perform iterative decoding for concatenated encoded data. Also, it may be possible to quickly decode concatenated encoded received data.
摘要翻译：提供了用于解码级联代码的装置及其方法，其可以基于相对于多个解码器的输出的似然值来提高级联代码的解码速度。解码级联代码的方法可以包括：计算级联编码的接收数据的似然值; 基于所计算的似然值对接收到的数据执行第一解码以生成第一解码数据; 对所述第一解码数据执行第二解码以产生第二解码数据; 以及基于所述第二解码数据来确定是否执行迭代解码。根据示例性实施例，可以直接管理级联解码数据的质量，从而准确地确定是否对级联编码数据执行迭代解码。此外，可以快速解码连接编码的接收数据。

19. 发明授权

US08607118B2 Iterative decoding method and apparatus 有权
标题翻译：迭代解码方法和装置
公开(公告)号：US08607118B2
公开(公告)日：2013-12-10
申请号：US12475640
申请日：2009-06-01
申请人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
发明人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
IPC分类号： H03M13/00
CPC分类号： H03M13/1105 , H03M13/136 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2906 , H03M13/3738 , H03M13/3753 , H04L1/0051 , H04L1/0057
摘要： An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.
摘要翻译：公开了一种迭代解码方法，并且包括相对于奇偶校验方程顺序执行多个迭代解码周期，直到奇偶校验方程被解析为止，或者在迭代次数的执行期间达到迭代解码周期的最大数量N 解码周期，在数据缓冲器中存储对应于最小数量的位错误的一组可变节点的最小估计值，并且当迭代解码周期数达到时，输出存储在数据缓冲器中的最小估计值作为最终解码结果 N.

20. 发明授权

US08281217B2 Memory devices and encoding and/or decoding methods 有权
标题翻译：存储器件和编码和/或解码方法
公开(公告)号：US08281217B2
公开(公告)日：2012-10-02
申请号：US12379746
申请日：2009-02-27
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong
IPC分类号： G11C29/00
CPC分类号： H03M13/2903 , G06F11/1072 , H03M13/29 , H03M13/353
摘要： Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword.
摘要翻译：提供存储器件和/或编码/解码方法。存储器件可以包括：存储器单元阵列; 内部解码器，被配置为向从存储器单元阵列读取的第一代码字应用基于第一通道的特性选择的第一解码方案，其中读取第一代码字以执行第一代码字的错误控制代码（ECC）解码代码字，并且应用于从存储单元阵列读取的第二码字，基于第二通道的特性选择的第二解码方案，其中读取第二码字以执行第二码字的ECC解码; 以及外部解码器，被配置为将外部解码方案应用于ECC解码的第一码字和ECC解码的第二码字，以执行第一码字和第二码字的ECC解码。

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