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11. 发明授权

US07797666B1 Systems and methods for mapping arbitrary logic functions into synchronous embedded memories 有权
标题翻译：将任意逻辑功能映射到同步嵌入式存储器中的系统和方法
公开(公告)号：US07797666B1
公开(公告)日：2010-09-14
申请号：US12244635
申请日：2008-10-02
申请人： Gordon Chiu , Deshanand Singh , Valavan Manohararajah , Stephen Brown
发明人： Gordon Chiu , Deshanand Singh , Valavan Manohararajah , Stephen Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.
摘要翻译：提供了将逻辑元件（“LE”）的逻辑功能映射到可编程逻辑器件（“PLD”）的同步嵌入式存储器块（“EMB”）的系统和方法。这种技术增加了可以适应PLD的逻辑量。如果区域节省很大，则可以选择较小的PLD来实现特定的电路。本发明的一个方面涉及用于识别可以映射到同步EMB中的逻辑顺序锥的方法。在确定用于映射到同步EMB中的顺序逻辑锥之后，可以根据需要选择，扩展，重构和重新定时，以实现映射。本发明的另一方面涉及用于处理同步EMB的架构限制的技术，诸如不能实现同步逻辑的异步行为。

12. 发明授权

US07509597B1 Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagrams 有权
标题翻译：使用二进制决策图在现场可编程门阵列上执行放置后功能分解的方法和装置
公开(公告)号：US07509597B1
公开(公告)日：2009-03-24
申请号：US11172007
申请日：2005-06-30
申请人： Valavan Manohararajah , Deshanand Singh , Stephen Brown
发明人： Valavan Manohararajah , Deshanand Singh , Stephen Brown
IPC分类号： G06G17/50
CPC分类号： G06F17/5054 , G06F17/5072
摘要： A method for designing a system on a field programmable gate array (FPGA) includes using binary decision diagrams (BDDs) to perform functional decomposition on a design for the system after placement.
摘要翻译：用于在现场可编程门阵列（FPGA）上设计系统的方法包括使用二进制决策图（BDD）对放置后的系统的设计执行功能分解。

13. 发明授权

US08201114B1 Method and apparatus for performing look up table unpacking and repacking for resynthesis 有权
标题翻译：执行查找表拆包和再包装以进行再合成的方法和装置
公开(公告)号：US08201114B1
公开(公告)日：2012-06-12
申请号：US12590933
申请日：2009-11-17
申请人： Valavan Manohararajah , Gordon Raymond Chiu , John Stuart Freeman
发明人： Valavan Manohararajah , Gordon Raymond Chiu , John Stuart Freeman
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A method for optimizing a system on a target device is disclosed. A LUT is unpacked to form a plurality of LUTs of a smaller size upon determining that the unpacking can satisfy one or more predefined objectives. The plurality of LUTs are repacked such that the design for the system is improved. Other embodiments are disclosed.
摘要翻译：公开了一种用于优化目标设备上的系统的方法。在确定拆包可以满足一个或多个预定义目标的情况下，LUT被解包以形成较小尺寸的多个LUT。多个LUT被重新包装，使得系统的设计得到改进。公开了其他实施例。

14. 发明授权

US07412677B1 Detecting reducible registers 有权
标题翻译：检测可还原寄存器
公开(公告)号：US07412677B1
公开(公告)日：2008-08-12
申请号：US11360739
申请日：2006-02-22
申请人： Valavan Manohararajah , Gordon R. Chiu , Deshanand Singh , Stephen Brown
发明人： Valavan Manohararajah , Gordon R. Chiu , Deshanand Singh , Stephen Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/504 , G06F2217/84
摘要： Reducible registers are determined to optimize a sequential circuit. A screening method tests one or more sets of registers where the registers of each set are assumed to satisfy a logic condition. The tests determine if the logic condition holds. If the logic condition of a set is found to be violated, the registers may be moved to another set having a different logic condition or removed completely. The registers remaining are potentially reducible. The reducibility of the registers is verified via Boolean analysis by verifying the logic conditions of a register set for each register. If a register does not pass verification, it then may be moved to a different set having a different logic condition or removed completely. The sets that pass verification are reducible.
摘要翻译：确定可减少寄存器以优化顺序电路。一种筛选方法测试一组或多组寄存器，其中假设每个寄存器的寄存器满足逻辑条件。测试确定逻辑条件是否成立。如果发现集合的逻辑条件被违反，则可以将寄存器移动到具有不同逻辑条件的另一集合或完全移除。剩余的寄存器是可以减少的。通过布尔分析来验证寄存器的可复原性，通过验证每个寄存器的寄存器集的逻辑条件。如果寄存器不通过验证，则可以将其移动到具有不同逻辑条件的不同集合或完全移除。通过验证的集合是可以减少的。

15. 发明授权

US07360190B1 Method and apparatus for performing retiming on field programmable gate arrays 有权
标题翻译：用于在现场可编程门阵列上执行重新定时的方法和装置
公开(公告)号：US07360190B1
公开(公告)日：2008-04-15
申请号：US10876709
申请日：2004-06-25
申请人： Deshanand Singh , Gabriel Quan , Terry Borer , Ian Chesal , Valavan Manohararajah , Karl Schabas , Stephen Brown
发明人： Deshanand Singh , Gabriel Quan , Terry Borer , Ian Chesal , Valavan Manohararajah , Karl Schabas , Stephen Brown
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072 , G06F17/5081
摘要： A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying registers on near-critical paths. The registers are moved to shorten lengths of one or more near-critical paths.
摘要翻译：利用现场可编程门阵列（FPGA）在目标设备上设计系统的方法包括识别近临界路径上的寄存器。移动寄存器以缩短一个或多个近临界路径的长度。

16. 发明授权

US07257800B1 Method and apparatus for performing logic replication in field programmable gate arrays 有权
标题翻译：用于在现场可编程门阵列中执行逻辑复制的方法和装置
公开(公告)号：US07257800B1
公开(公告)日：2007-08-14
申请号：US10806617
申请日：2004-06-24
申请人： Deshanand Singh , Gabriel Quan , Terry Borer , Valavan Manohararajah , Paul McHardy , Ivan Hamer , Karl Schabas , Kevin Chan
发明人： Deshanand Singh , Gabriel Quan , Terry Borer , Valavan Manohararajah , Paul McHardy , Ivan Hamer , Karl Schabas , Kevin Chan
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device utilizing field programmable gate arrays is disclosed. A design is synthesized for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. Components to replicate are identified in response to criticality determined from the placement locations.
摘要翻译：公开了一种使用现场可编程门阵列在目标设备上设计系统的方法。为系统合成了一个设计。设计中的组件映射到目标设备上的资源。确定目标设备上的组件的位置位置。根据从放置位置确定的关键性来识别要复制的组件。

17. 发明申请

US20130257476A1 INTEGRATED CIRCUITS WITH MULTI-STAGE LOGIC REGIONS 有权
标题翻译：具有多级逻辑区域的集成电路
公开(公告)号：US20130257476A1
公开(公告)日：2013-10-03
申请号：US13434847
申请日：2012-03-29
申请人： David Cashman , David Lewis , Valavan Manohararajah
发明人： David Cashman , David Lewis , Valavan Manohararajah
IPC分类号： H03K19/20
CPC分类号： H03K19/17728
摘要： A programmable logic region on a programmable integrated circuit may include a first set of look-up tables that receive programmable logic region input signals and a second set of look-up tables that produce programmable logic region output signals. Multiplexer circuitry may be interposed between the first and second sets of look-up tables. The multiplexer circuitry may receive the programmable logic region input signals in parallel with the output signals from the first set of look-up tables and may provide corresponding selected signals to the second set of look-up tables. The programmable logic region input signals may be shared by the first and second sets of look-up tables. Logic circuitry may be coupled to outputs of the first and second sets of look-up tables. The logic circuitry may be configured to logically combine output signals from the first and second sets of look-up tables.
摘要翻译：可编程集成电路上的可编程逻辑区域可以包括接收可编程逻辑区域输入信号的第一组查询表和产生可编程逻辑区域输出信号的第二组查找表。多路复用器电路可以插入在第一组和第二组查找表之间。多路复用器电路可以与来自第一组查找表的输出信号并行地接收可编程逻辑区域输入信号，并且可以向第二组查找表提供相应的所选择的信号。可编程逻辑区域输入信号可以由第一组和第二组查找表共享。逻辑电路可以耦合到第一组和第二组查找表的输出。逻辑电路可以被配置为逻辑地组合来自第一组和第二组查找表的输出信号。

18. 发明授权

US08847624B1 Method and system for operating a circuit 有权
标题翻译：操作电路的方法和系统
公开(公告)号：US08847624B1
公开(公告)日：2014-09-30
申请号：US13358449
申请日：2012-01-25
申请人： Valavan Manohararajah
发明人： Valavan Manohararajah
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17728
摘要： Operation of a programmable circuit is described. A circuit including a plurality of multiplexers may be used to perform at least one operation on a plurality of signals. The at least one operation may be performed by the multiplexers using a select line coupled to or shared by the multiplexers. Each input of the circuit may couple to a respective output of a plurality of logic elements. As such, the circuit may be used to perform at least one operation on signals supplied from a plurality of logic elements, thereby expanding the functionality of at least one logic element coupled to the circuit and/or increasing the number of logic elements and other resources available for implementing user designs or performing other functions.
摘要翻译：描述可编程电路的操作。可以使用包括多个多路复用器的电路来对多个信号执行至少一个操作。所述至少一个操作可以由多路复用器使用耦合到或由多路复用器共享的选择线来执行。电路的每个输入可以耦合到多个逻辑元件的相应输出。这样，电路可以用于对从多个逻辑元件提供的信号执行至少一个操作，从而扩展耦合到电路的至少一个逻辑元件的功能和/或增加逻辑元件和其他资源的数量可用于实现用户设计或执行其他功能。

19. 发明申请

US20110283250A1 Method and apparatus for performing asynchronous and synchronous reset removal during synthesis 有权
标题翻译：在合成期间执行异步和同步复位去除的方法和装置
公开(公告)号：US20110283250A1
公开(公告)日：2011-11-17
申请号：US12800227
申请日：2010-05-11
申请人： Valavan Manohararajah
发明人： Valavan Manohararajah
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for designing a system on a target device is disclosed. A system is synthesized by converting a high level description of the system into gates, registers, and reset circuitry. An analysis is performed to identify and remove redundant reset circuitry. The system is optimized after the redundant reset circuitry has been removed. Other embodiments are disclosed.
摘要翻译：公开了一种在目标设备上设计系统的方法。通过将系统的高级描述转换为门，寄存器和复位电路来合成系统。执行分析以识别和去除冗余复位电路。在冗余复位电路被去除后，系统进行了优化。公开了其他实施例。

20. 发明申请

US20180349098A1 METHODS AND APPARATUS FOR SEQUENCING MULTIPLY-ACCUMULATE OPERATIONS 审中-公开
公开(公告)号：US20180349098A1
公开(公告)日：2018-12-06
申请号：US15988458
申请日：2018-05-24
申请人： Valavan Manohararajah
发明人： Valavan Manohararajah
IPC分类号： G06F7/544
CPC分类号： G06F7/5443 , G06F2207/3868
摘要： An integrated circuit may have specialized processing blocks that are configurable to operate as arithmetic operators that may implement, amongst other functions, multiplication and multiply-accumulation operations in a first mode. In a second mode, a sequencer circuit may provide data signals and control signals to the specialized processing blocks such that the specialized processing block operates as a signal processing device that handles signals in a given sequence. For example, the sequencer circuit may control the signal arrival at the specialized processing block and the configuration of the configurable circuitry in the specialized processing block. In certain embodiments, the sequencer circuit and the specialized processing block may implement finite impulse response (FIR) filters.

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