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11. 发明授权

US07733109B2 Test structure for resistive open detection using voltage contrast inspection and related methods 有权
标题翻译：使用电压对比检查和相关方法进行电阻式开路检测的测试结构
公开(公告)号：US07733109B2
公开(公告)日：2010-06-08
申请号：US11872213
申请日：2007-10-15
申请人： Ishtiaq Ahsan , Mark B. Ketchen , Kevin McStay , Oliver D. Patterson
发明人： Ishtiaq Ahsan , Mark B. Ketchen , Kevin McStay , Oliver D. Patterson
IPC分类号： G01R31/302
CPC分类号： G01R31/2853 , G01R31/307 , H01L22/14 , H01L22/34
摘要： A test structure for resistive open detection using voltage contrast (VC) inspection and method for using such structure are disclosed. The test structure may include a comparator within the IC chip for comparing a resistance value of a resistive element under test to a reference resistance and outputting a result of the comparing that indicates whether the resistive open exists in the resistive element under test, wherein the result is detectable by the voltage contrast inspection.
摘要翻译：公开了使用电压对比（VC）检查的电阻式开路检测的测试结构和使用这种结构的方法。测试结构可以包括IC芯片内的比较器，用于将被测电阻元件的电阻值与参考电阻进行比较，并输出比较结果，指示电阻开路是否存在于被测电阻元件中，其中结果可通过电压对比度检测来检测。

12. 发明申请

US20090096461A1 TEST STRUCTURE AND METHOD FOR RESISTIVE OPEN DETECTION USING VOLTAGE CONTRAST INSPECTION 有权
标题翻译：使用电压对比检查的电阻式开路检测的测试结构和方法
公开(公告)号：US20090096461A1
公开(公告)日：2009-04-16
申请号：US11872213
申请日：2007-10-15
申请人： Ishtiaq Ahsan , Mark B. Ketchen , Kevin McStay , Oliver D. Patterson
发明人： Ishtiaq Ahsan , Mark B. Ketchen , Kevin McStay , Oliver D. Patterson
IPC分类号： G01R31/265
CPC分类号： G01R31/2853 , G01R31/307 , H01L22/14 , H01L22/34
摘要： A test structure for resistive open detection using voltage contrast (VC) inspection and method for using such structure are disclosed. The test structure may include a comparator within the IC chip for comparing a resistance value of a resistive element under test to a reference resistance and outputting a result of the comparing that indicates whether the resistive open exists in the resistive element under test, wherein the result is detectable by the voltage contrast inspection.
摘要翻译：公开了使用电压对比（VC）检查的电阻式开路检测的测试结构和使用这种结构的方法。测试结构可以包括IC芯片内的比较器，用于将被测电阻元件的电阻值与参考电阻进行比较，并输出比较结果，指示电阻开路是否存在于被测电阻元件中，其中结果可通过电压对比度检测来检测。

13. 发明申请

US20070087593A1 STRUCTURE FOR MONITORING SEMICONDUCTOR POLYSILICON GATE PROFILE 有权
标题翻译：用于监测半导体多晶硅门型材的结构
公开(公告)号：US20070087593A1
公开(公告)日：2007-04-19
申请号：US11539231
申请日：2006-10-06
申请人： Ishtiaq Ahsan , Edward Maciejewski
发明人： Ishtiaq Ahsan , Edward Maciejewski
IPC分类号： H05K1/00 , H01R12/00
CPC分类号： H01L22/34
摘要： Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of bottom width to average width of cross sectional area of the same polysilicon line.
摘要翻译：通过测试结构（1）测量相同多晶硅线（2）的横截面积的底部宽度和平均宽度与两个测量值相关联的测试结构来增强多晶硅线的轮廓漂移的检测，并且（3）比较这与以前的相同多晶硅线的横截面积的底宽与平均宽度的相关性的相关性。

14. 发明申请

US20120119778A1 POST SILICIDE TESTING FOR REPLACEMENT HIGH-K METAL GATE TECHNOLOGIES 有权
标题翻译：用于更换高K金属门技术的硅胶测试
公开(公告)号：US20120119778A1
公开(公告)日：2012-05-17
申请号：US12946875
申请日：2010-11-16
申请人： Ishtiaq Ahsan , David M. Fried , Lidor Goren , Jiun-Hsin Liao
发明人： Ishtiaq Ahsan , David M. Fried , Lidor Goren , Jiun-Hsin Liao
IPC分类号： G01R31/26 , H01L23/58 , H01L21/66
CPC分类号： H01L22/34 , G01R31/2621
摘要： A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the active area of the IC device, in electrical contact with the one or more probe pads; one or more second conductive lines formed at a gate conductor level of the IC device, in electrical contact with the one or more first conductive lines; and a gate electrode structure to be tested in electrical contact with the one or more second conductive lines; wherein the electrical contact between the one or more second conductive lines and the one or more first conductive lines is facilitated by a localized dielectric breakdown of a gate dielectric material disposed between the one or more second conductive lines and the one or more first conductive lines.
摘要翻译：用于测试IC器件中的晶体管栅极结构的测试结构包括形成在IC器件的有效区域上的一个或多个探针焊盘; 一个或多个第一导电线形成在所述IC器件的有源区，与所述一个或多个探针焊盘电接触; 形成在所述IC器件的栅极导体级的一个或多个第二导线，与所述一个或多个第一导线电接触; 以及要与所述一个或多个第二导线电接触测试的栅电极结构; 其中所述一个或多个第二导电线与所述一个或多个第一导电线之间的电接触由设置在所述一个或多个第二导电线与所述一个或多个第一导电线之间的栅极电介质材料的局部介电击穿来促进。

15. 发明授权

US07612371B2 Structure to monitor arcing in the processing steps of metal layer build on silicon-on-insulator semiconductors 失效
标题翻译：在绝缘体上半导体上构建金属层的处理步骤中的电弧放电结构
公开(公告)号：US07612371B2
公开(公告)日：2009-11-03
申请号：US11306944
申请日：2006-01-17
申请人： Ishtiaq Ahsan , Christine M. Bunke , Stephen E. Greco
发明人： Ishtiaq Ahsan , Christine M. Bunke , Stephen E. Greco
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge accumulating antenna structure across parallel plate electrodes. When an arc of a predetermined sufficient strength is present, the macro will experience a voltage breakdown that is measurable as a short. The parallel plate electrodes may both be at the floating potential of the microchip to monitor CMP-induced or lithographic-induced charge failure mechanisms, or have one electrode electrically connected to a ground potential structure to capture charge induced damage, hence having the capability to differentiate between the two.
摘要翻译：本发明通过可以容易地结合在晶片上的检测结构来检测电荷引起的缺陷，以检测半导体处理线的后端处理线路中的电荷引起的损伤。测试宏被设计成将电弧从电荷累积天线结构引导到跨平行板电极的另一电荷累积天线结构。当存在预定足够强度的电弧时，宏将经历可测量的短路电压击穿。平行板电极都可以处于微芯片的浮动电位，以监测CMP诱导或光刻诱发的电荷失效机理，或者将一个电极电连接到地电位结构以捕获电荷引起的损伤，因此具有区别的能力两者之间。

16. 发明授权

US07515502B1 Memory array peripheral structures and use 失效
标题翻译：内存阵列外设结构和使用
公开(公告)号：US07515502B1
公开(公告)日：2009-04-07
申请号：US11856964
申请日：2007-09-18
申请人： Ishtiaq Ahsan , Louis Lu-Chen Hsu , Xu Ouyang
发明人： Ishtiaq Ahsan , Louis Lu-Chen Hsu , Xu Ouyang
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C5/02 , G11C5/06 , G11C29/006 , G11C29/24 , G11C29/48 , G11C29/808 , G11C29/816 , G11C29/838
摘要： A method for using photolithographic dummy memory cells arranged in rings around a set of primary memory cells as test structures and as redundant memory cells. Also circuits and structures of memory arrays having multiple-use dummy memory cells.
摘要翻译：一种使用设置在作为测试结构的一组主存储器单元周围的环的光刻虚拟存储单元的方法和作为冗余存储单元的方法。还有具有多次使用的虚拟存储器单元的存储器阵列的电路和结构。

17. 发明授权

US07408421B2 Determining thermal absorption using ring oscillator 有权
标题翻译：使用环形振荡器确定热吸收
公开(公告)号：US07408421B2
公开(公告)日：2008-08-05
申请号：US11428622
申请日：2006-07-05
申请人： Ishtiaq Ahsan , Edward P. Maciejewski , Noah D. Zamdmer
发明人： Ishtiaq Ahsan , Edward P. Maciejewski , Noah D. Zamdmer
IPC分类号： H03B27/00
CPC分类号： H03K3/0315 , G01K7/32
摘要： A device and method for determining a thermal absorption of a part of an integrated circuit (IC) are provided. A specially designed ring oscillator including a non-silicided poly-silicon resistor is used for the determination. The parameters of the ring oscillator are designed/tuned so that a delay of the ring oscillator varies predominantly with a variation in a resistance of the non-silicided poly-silicon resistor. The dimensions of the non-silicided poly-silicon resistor are large enough so that the resistance of the non-silicided poly-silicon resistor is immune to the small process variations of the poly-silicon length and width. The resistance of the non-silicided poly-silicon resistor varies with the thermal absorption of the part of the IC. As such, the thermal absorption of the part of the IC may be determined based on the delay of the ring oscillator.
摘要翻译：提供了一种用于确定集成电路（IC）的一部分的热吸收的装置和方法。使用特殊设计的环形振荡器，其包括非硅化多晶硅电阻器用于测定。环形振荡器的参数被设计/调谐，使得环形振荡器的延迟主要由非硅化多晶硅电阻器的电阻变化而变化。非硅化多晶硅电阻器的尺寸足够大，使得非硅化多晶硅电阻器的电阻不受多硅长度和宽度的小工艺变化的影响。非硅化多晶硅电阻的电阻随着IC部分的热吸收而变化。因此，IC的一部分的热吸收可以基于环形振荡器的延迟来确定。

18. 发明授权

US07396694B2 Structure for monitoring semiconductor polysilicon gate profile 有权
标题翻译：用于监测半导体多晶硅栅极分布的结构
公开(公告)号：US07396694B2
公开(公告)日：2008-07-08
申请号：US11539231
申请日：2006-10-06
申请人： Ishtiaq Ahsan , Edward P. Maciejewski
发明人： Ishtiaq Ahsan , Edward P. Maciejewski
IPC分类号： H01L21/66
CPC分类号： H01L22/34
摘要： Detection of a profile drift of a polysilicon line is enhanced by a test structure that (1) measures a bottom width and an average width of a cross sectional area of the same polysilicon line (2) correlates the two measurements, and (3) compares such correlation with a previous correlation of bottom width to average width of cross sectional area of the same polysilicon line.
摘要翻译：通过测试结构（1）测量相同多晶硅线（2）的横截面积的底部宽度和平均宽度与两个测量值相关联的测试结构来增强多晶硅线的轮廓漂移的检测，并且（3）比较这与以前的相同多晶硅线的横截面积的底宽与平均宽度的相关性的相关性。

19. 发明申请

US20080007354A1 DETERMINING THERMAL ABSORPTION USING RING OSCILLATOR 有权
标题翻译：使用振荡器确定热吸收
公开(公告)号：US20080007354A1
公开(公告)日：2008-01-10
申请号：US11428622
申请日：2006-07-05
申请人： Ishtiaq Ahsan , Edward P. Maciejewski , Noah D. Zamdmer
发明人： Ishtiaq Ahsan , Edward P. Maciejewski , Noah D. Zamdmer
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , G01K7/32
摘要： A device and method for determining a thermal absorption of a part of an integrated circuit (IC) are provided. A specially designed ring oscillator including an un-silicided poly-silicon resistor is used for the determination. The parameters of the ring oscillator are designed/tuned so that a delay of the ring oscillator varies predominantly with a variation in a resistance of the un-silicided poly-silicon resistor. The dimensions of the un-silicided poly-silicon resistor are large enough so that the resistance of the un-silicided poly-silicon resistor is immune to the small process variations of the poly-silicon length and width. The resistance of the un-silicided poly-silicon resistor varies with the thermal absorption of the part of the IC. As such, the thermal absorption of the part of the IC may be determined based on the delay of the ring oscillator.
摘要翻译：提供了一种用于确定集成电路（IC）的一部分的热吸收的装置和方法。使用特殊设计的环形振荡器，其包括非硅化多晶硅电阻器用于测定。环形振荡器的参数被设计/调谐，使得环形振荡器的延迟主要随着未硅化多晶硅电阻器的电阻的变化而变化。未硅化多晶硅电阻器的尺寸足够大，使得未硅化的多晶硅电阻器的电阻不受多硅长度和宽度的小工艺变化的影响。未硅化的多晶硅电阻器的电阻随着IC部分的热吸收而变化。因此，IC的一部分的热吸收可以基于环形振荡器的延迟来确定。

20. 发明申请

US20070164421A1 STRUCTURE TO MONITOR ARCING IN THE PROCESSING STEPS OF METAL LAYER BUILD ON SILICON-ON-INSULATOR SEMICONDUCTORS 失效
标题翻译：金属绝缘子半导体制造金属层加工步骤中的结构监测
公开(公告)号：US20070164421A1
公开(公告)日：2007-07-19
申请号：US11306944
申请日：2006-01-17
申请人： Ishtiaq Ahsan , Christine Bunke , Stephen Greco
发明人： Ishtiaq Ahsan , Christine Bunke , Stephen Greco
IPC分类号： H01L23/52
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： The present invention addresses detection of charge-induced defects through test structures that can be easily incorporated on a wafer to detect charge-induced damage in the back-end-of-line processing of a semiconductor processing line. A test macro is designed to induce an arc from a charge accumulating antenna structure to another charge accumulating antenna structure across parallel plate electrodes. When an arc of a predetermined sufficient strength is present, the macro will experience a voltage breakdown that is measurable as a short. The parallel plate electrodes may both be at the floating potential of the microchip to monitor CMP-induced or lithographic-induced charge failure mechanisms, or have one electrode electrically connected to a ground potential structure to capture charge induced damage, hence having the capability to differentiate between the two.
摘要翻译：本发明通过可以容易地结合在晶片上的检测结构来检测电荷引起的缺陷，以检测半导体处理线的后端处理线路中的电荷引起的损伤。测试宏被设计成将电弧从电荷累积天线结构引导到跨平行板电极的另一电荷累积天线结构。当存在预定足够强度的电弧时，宏将经历可测量的短路电压击穿。平行板电极都可以处于微芯片的浮动电位，以监测CMP诱导或光刻诱发的电荷失效机理，或者将一个电极电连接到地电位结构以捕获电荷引起的损伤，因此具有区别的能力两者之间。

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