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11. 发明申请

US20120110542A1 METHOD TO SCALE DOWN IC LAYOUT 有权
标题翻译：降低IC布局的方法
公开(公告)号：US20120110542A1
公开(公告)日：2012-05-03
申请号：US13347711
申请日：2012-01-11
申请人： Hsien-Chang Chang
发明人： Hsien-Chang Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method scales down an integrated circuit layout structure without substantially jeopardizing electronic characteristics of devices. First, a conductive line set includes a first conductive line and a second conductive line respectively passing through a first region and a second region. Second, a sizing-down operation is performed so that the first conductive line and the second conductive line respectively have a first region scaled-down line width, a first region scaled-down space and a first region scaled-down pitch in the first region as well as selectively have a second region original line width, a second region scaled-down space and a second region scaled-down pitch in the second region. The first region scaled-down line width and the second region original line width are substantially different from each other.
摘要翻译：一种方法可以缩小集成电路布局结构，而不会基本上危及设备的电子特性。首先，导线组包括分别通过第一区域和第二区域的第一导线和第二导线。其次，执行施胶操作，使得第一导电线和第二导线在第一区域中分别具有第一区域缩小线宽度，第一区域缩小空间和第一区域缩小间距以及在第二区域中选择性地具有第二区域原始线宽度，第二区域缩小空间和第二区域缩小间距。第一区域缩小线宽度和第二区域原始线宽度彼此大不相同。

12. 发明申请

US20100320558A1 CIRCUIT LAYOUT STRUCTURE AND METHOD TO SCALE DOWN IC LAYOUT 审中-公开
标题翻译：电路布局结构和缩小IC布局的方法
公开(公告)号：US20100320558A1
公开(公告)日：2010-12-23
申请号：US12487631
申请日：2009-06-18
申请人： Hsien-Chang Chang
发明人： Hsien-Chang Chang
IPC分类号： H01L27/02 , G06F17/50
CPC分类号： G06F17/5068
摘要： A circuit layout structure includes a substrate including a first region and a second region, and a set of conductive lines including a first conductive line and a second conductive line which respectively pass through the first region and the second region, wherein a variable spacing lies between the first conductive line and the second conductive line and the first conductive line and the second conductive line selectively have a first region line width and a second region line width so that the first region line width and the second region line width are substantially different.
摘要翻译：电路布局结构包括包括第一区域和第二区域的衬底以及分别穿过第一区域和第二区域的第一导电线和第二导电线的一组导线，其中可变间隔位于第一导线和第二导线以及第一导线和第二导线选择性地具有第一区域线宽度和第二区域线宽度，使得第一区域线宽度和第二区域线宽度基本上不同。

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