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11. 发明授权

US08138797B1 Integrated circuits with asymmetric pass transistors 有权
标题翻译：具有不对称传输晶体管的集成电路
公开(公告)号：US08138797B1
公开(公告)日：2012-03-20
申请号：US12790660
申请日：2010-05-28
申请人： Jun Liu , Albert Ratnakumar , Mark T. Chan , Irfan Rahim
发明人： Jun Liu , Albert Ratnakumar , Mark T. Chan , Irfan Rahim
IPC分类号： H01L25/00 , H03K19/00
CPC分类号： H01L21/823418 , H01L21/324 , H01L21/823814 , H01L27/082 , H01L27/088 , H01L29/1083 , H01L29/6653 , H01L29/66659
摘要： Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.
摘要翻译：不对称晶体管，例如不对称传输晶体管可以形成在集成电路上。不对称晶体管可以具有栅极结构。可以在每个晶体管栅极结构的相对侧上的源极漏极中形成对称的袋状植入物。选择性加热可用于不对称地扩散植入物。可以通过在半导体衬底上图案化栅极结构来实现选择性加热，使得相邻栅极结构之间的间隔变化。给定的栅极结构可以位于与给定栅极结构不同的相应距离处间隔开的第一和第二相邻栅极结构之间。较大的栅极结构间隔导致比较小栅极结构间隔更大的衬底温度升高。在较大的温度上升的情况下，口袋植入物在衬底的部分扩散，产生不对称晶体管。不对称传输晶体管可以由来自存储器元件的静态控制信号来控制，以实现诸如可编程多路复用器之类的电路。

12. 发明授权

US08995175B1 Memory circuit with PMOS access transistors 有权
标题翻译：具有PMOS存取晶体管的存储电路
公开(公告)号：US08995175B1
公开(公告)日：2015-03-31
申请号：US13350575
申请日：2012-01-13
申请人： Jun Liu , Irfan Rahim , Yanzhong Xu , Andy L. Lee
发明人： Jun Liu , Irfan Rahim , Yanzhong Xu , Andy L. Lee
IPC分类号： G11C11/412 , G11C5/14
CPC分类号： G11C5/14 , G11C11/412 , G11C11/418
摘要： A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one implementation, the memory circuit further includes a bias clamp transistor coupled to the memory storage unit.
摘要翻译：描述了一种存储器电路，其包括存储器存储单元和耦合到存储器存储单元的存取晶体管，其中存取晶体管包括PMOS晶体管。在一个实现中，存储器电路还包括耦合到存储器存储单元的偏置钳位晶体管。

13. 发明申请

US20120235662A1 VERY LOW VOLTAGE REFERENCE CIRCUIT 有权
标题翻译：非常低的电压参考电路
公开(公告)号：US20120235662A1
公开(公告)日：2012-09-20
申请号：US13051648
申请日：2011-03-18
申请人： Albert Ratnakumar , Qi Xiang , Simardeep Maangat , Jun Liu
发明人： Albert Ratnakumar , Qi Xiang , Simardeep Maangat , Jun Liu
IPC分类号： G05F3/02
CPC分类号： G05F3/30
摘要： A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt.
摘要翻译：低压参考电路可以具有一对半导体器件。每个半导体器件可以具有n型半导体区域，n型半导体区域中的n +区域，金属栅极和介于金属栅极和n型半导体区域之间的栅极绝缘体，载流子穿过该栅极绝缘体。金属栅极可以具有与p型多晶硅相匹配的功函数。栅极绝缘体可以具有小于约25埃的厚度。金属栅极可以形成用于半导体器件的第一端子，并且n +区域和n型半导体区域可以形成用于半导体器件的第二端子。第二端子可以接地。偏置电路可以使用第一端子来向半导体器件提供不同的电流，并且可以将相应的参考输出电压提供在小于1伏的值。

14. 发明授权

US08530976B1 Memory element transistors with reversed-workfunction gate conductors 有权
标题翻译：具有反功能栅极导体的存储元件晶体管
公开(公告)号：US08530976B1
公开(公告)日：2013-09-10
申请号：US13113896
申请日：2011-05-23
申请人： Albert Ratnakumar , Qi Xiang , Jun Liu
发明人： Albert Ratnakumar , Qi Xiang , Jun Liu
IPC分类号： H01L21/70
CPC分类号： H01L29/7833 , H01L21/823842 , H01L27/1104
摘要： Integrated circuits may be provided that include memory elements that produce output control signals and corresponding programmable logic circuitry that receives the output control signals from the memory elements. The memory elements may include bistable storage elements formed from circuits such as cross-coupled inverters. The inverters may include n-channel metal-oxide-semiconductor transistors with p-metal gate conductors and n-channel metal-oxide-semiconductor transistors with p-metal gate conductors. These gate conductor assignments are the reverse of the gate conductor assignments used in the n-channel and p-channel transistors in other circuitry such as the programmable logic circuitry. The reversed gate conductor assignments increase the threshold voltages of the transistors in the memory elements to improve reliability in scenarios in which the memory elements are overdriving pass transistors in the programmable logic circuitry.
摘要翻译：可以提供集成电路，其包括产生输出控制信号的存储器元件和从存储器元件接收输出控制信号的相应的可编程逻辑电路。存储器元件可以包括由诸如交叉耦合的反相器的电路形成的双稳态存储元件。反相器可以包括具有p金属栅极导体的n沟道金属氧化物半导体晶体管和具有p型金属栅极导体的n沟道金属氧化物半导体晶体管。这些栅极导体分配与在诸如可编程逻辑电路的其它电路中的n沟道和p沟道晶体管中使用的栅极导体分配相反。反向栅极导体分配增加存储器元件中的晶体管的阈值电压，以提高存储元件过驱动可编程逻辑电路中的通过晶体管的情况下的可靠性。

15. 发明授权

US08264214B1 Very low voltage reference circuit 有权
标题翻译：极低电压参考电路
公开(公告)号：US08264214B1
公开(公告)日：2012-09-11
申请号：US13051648
申请日：2011-03-18
申请人： Albert Ratnakumar , Qi Xiang , Simardeep Maangat , Jun Liu
发明人： Albert Ratnakumar , Qi Xiang , Simardeep Maangat , Jun Liu
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A low-voltage reference circuit may have a pair of semiconductor devices. Each semiconductor device may have an n-type semiconductor region, an n+ region in the n-type semiconductor region, a metal gate, and a gate insulator interposed between the metal gate and the n-type semiconductor region through which carriers tunnel. The metal gate may have a work function matching that of p-type polysilicon. The gate insulator may have a thickness of less than about 25 angstroms. The metal gate may form a first terminal for the semiconductor device and the n+ region and n-type semiconductor region may form a second terminal for the semiconductor device. The second terminals may be coupled to ground. A biasing circuit may use the first terminals to supply different currents to the semiconductor devices and may provide a corresponding reference output voltage at a value that is less than one volt.
摘要翻译：低压参考电路可以具有一对半导体器件。每个半导体器件可以具有n型半导体区域，n型半导体区域中的n +区域，金属栅极和介于金属栅极和n型半导体区域之间的栅极绝缘体，载流子穿过该栅极绝缘体。金属栅极可以具有与p型多晶硅相匹配的功函数。栅极绝缘体可以具有小于约25埃的厚度。金属栅极可以形成用于半导体器件的第一端子，并且n +区域和n型半导体区域可以形成用于半导体器件的第二端子。第二端子可以接地。偏置电路可以使用第一端子来向半导体器件提供不同的电流，并且可以将相应的参考输出电压提供在小于1伏的值。

16. 发明授权

US08649209B1 Memory element circuitry with reduced oxide definition width 有权
标题翻译：具有降低氧化物界定宽度的存储元件电路
公开(公告)号：US08649209B1
公开(公告)日：2014-02-11
申请号：US13072530
申请日：2011-03-25
申请人： Jun Liu , Qi Xiang
发明人： Jun Liu , Qi Xiang
IPC分类号： G11C11/00
CPC分类号： H01L29/78 , G11C11/412
摘要： Integrated circuits with memory circuitry are provided. The memory circuitry may include memory cell transistors and associated pass transistors. The memory cell transistors and the pass transistors may be formed using multiple strips of oxide definition (OD) regions coupled in parallel. The multiple OD strips may have reduced widths. The ratio of the distance from adjacent OD strips to a given OD strip to the width of the given OD strip may be at least 0.5. Forming memory circuitry transistors using this multi-strip arrangement may provide increased levels of stress that improve transistor performance. Each OD strip may have a reduced width that still satisfies fabrication design rules. Forming OD regions having reduced width allows the pass transistors to be overdriven at higher voltage levels to further improve transistor performance.
摘要翻译：提供了具有存储器电路的集成电路。存储器电路可以包括存储器单元晶体管和相关联的传输晶体管。存储单元晶体管和传输晶体管可以使用并联耦合的多个氧化物定义（OD）区段形成。多个OD条可以具有减小的宽度。从相邻OD条到给定OD条的距离与给定OD条的宽度的比可以至少为0.5。使用这种多条布置形成存储器电路晶体管可以提供提高晶体管性能的增加的应力水平。每个OD条可以具有仍然满足制造设计规则的减小的宽度。形成具有减小的宽度的OD区域允许传输晶体管在更高的电压电平下被过载驱动以进一步提高晶体管的性能。

17. 发明授权

US08218353B1 Memory element circuitry with stressed transistors 有权
标题翻译：具有应力晶体管的存储元件电路
公开(公告)号：US08218353B1
公开(公告)日：2012-07-10
申请号：US12561236
申请日：2009-09-16
申请人： Jun Liu , Shankar Sinha , Qi Xiang , Yow-Juang Liu
发明人： Jun Liu , Shankar Sinha , Qi Xiang , Yow-Juang Liu
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Integrated circuits with memory elements are provided. The memory elements may be arranged in a memory block. The memory block may include cross-coupled inverters that store data. The stored data may be used to program pass transistors. Transistors in the memory block may be stressed. Depending on the type of stress-inducing layer used, a tensile stress or a compressive stress may be built in into the transistors. Stressed transistors may help improve the routing speed of the memory block. Stressed transistors may be implemented using dual gate-oxide process.
摘要翻译：提供具有存储元件的集成电路。存储器元件可以被布置在存储器块中。存储器块可以包括存储数据的交叉耦合的反相器。存储的数据可用于编程传输晶体管。存储器块中的晶体管可能受到压力。根据所使用的应力诱导层的类型，可以将内部的拉伸应力或压应力内置到晶体管中。受压的晶体管可能有助于提高存储器块的布线速度。可以使用双栅极氧化工艺来实施受压晶体管。

18. 外观设计

USD1025525S1 Bed vacuum cleaner 有权
公开(公告)号：USD1025525S1
公开(公告)日：2024-04-30
申请号：US29850874
申请日：2022-08-24
申请人： Jun Liu
设计人： Jun Liu
摘要： FIG. 1 is a top perspective view of a bed vacuum cleaner, showing my new design;
FIG. 2 is a bottom perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a rear view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top view thereof; and,
FIG. 8 is a bottom view thereof.
It is mainly composed of HEPA Filter, high-frequency tapping, vacuum motor, and visual trash can. It combines three functions of purple light, polaroid and vacuuming to absorb particles such as hair, pollen, dust, dander, etc. it is suitable for cleaning beds, sofas and other fabric products.
The broken lines in the drawings illustrate the portions of the bed vacuum cleaner, which form no part of the claimed design.

19. 发明授权

US10906934B2 Protein purification methods 有权
公开(公告)号：US10906934B2
公开(公告)日：2021-02-02
申请号：US14007610
申请日：2012-03-23
申请人： Arick Brown , Junyan Ji , Jun Liu , Yuchang John Wang
发明人： Arick Brown , Junyan Ji , Jun Liu , Yuchang John Wang
IPC分类号： C07K1/34 , C12N7/00 , C07K16/00
摘要： The invention provides methods of reducing fouling of ultrafiltration membranes in processes wherein virus particles are removed from aqueous solutions comprising virus particles and at least one protein by adding a surfactant or non-surfactant, non-ionic agent to the aqueous solution prior to filtration. The invention also provides methods to dissociate protein aggregates or to reduce the formation of protein aggregates by adding a surfactant or non-surfactant, non-ionic agent to the protein solution.

20. 发明授权

US10673069B2 Hybrid anodes for energy storage devices 审中-公开
公开(公告)号：US10673069B2
公开(公告)日：2020-06-02
申请号：US13532206
申请日：2012-06-25
申请人： Jun Liu , Jie Xiao , Cheng Huang
发明人： Jun Liu , Jie Xiao , Cheng Huang
IPC分类号： H01M4/38 , H01M4/587 , H01M4/485 , H01M4/58 , H01M10/0525 , H01M4/40 , H01M4/13
摘要： Energy storage devices having hybrid anodes can address at least the problems of active material consumption and anode passivation that can be characteristic of traditional batteries. The energy storage devices each have a cathode separated from the hybrid anode by a separator. The hybrid anode includes a carbon electrode connected to a metal electrode, thereby resulting in an equipotential between the carbon and metal electrodes.

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