专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20200159691A1 RELIABILITY-AWARE RUNTIME OPTIMAL PROCESSOR CONFIGURATION 审中-公开
公开(公告)号：US20200159691A1
公开(公告)日：2020-05-21
申请号：US16194247
申请日：2018-11-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Karthik V. Swaminathan , Ramon Bertran Monfort , Alper Buyuktosunoglu , Pradip Bose , Nandhini Chandramoorthy , Chen-Yong Cher
IPC分类号： G06F15/78 , G06F1/26
摘要： A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (Vdd), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.

12. 发明授权

US10585753B2 Checkpoint triggering in a computer system 有权
公开(公告)号：US10585753B2
公开(公告)日：2020-03-10
申请号：US16033274
申请日：2018-07-12
申请人： International Business Machines Corporation
发明人： Chen-Yong Cher
IPC分类号： G06F11/14 , G06F11/30 , G06F11/34
摘要： According to an aspect, a method for triggering creation of a checkpoint in a computer system includes executing a task in a processing node of the computer system. A monitoring block size is determined for the checkpoint. A checkpoint interval is determined based on the monitoring block size, a checkpoint bandwidth, and a failure rate of the computer system. Based on determining that the checkpoint interval has elapsed, the checkpoint including state data of the task is created to enable restarting execution of the task upon a restart operation. The state data of the checkpoint is restored from a memory responsive to detecting an error condition at the processing node. Execution of the task is restarted in the processing node based on the state data restored from the memory.

13. 发明授权

US10365702B2 Autonomic supply voltage compensation for degradation of circuits over circuit lifetime 有权
公开(公告)号：US10365702B2
公开(公告)日：2019-07-30
申请号：US15482917
申请日：2017-04-10
申请人： International Business Machines Corporation
发明人： Chen-Yong Cher , Pierce I Chuang , Keith A Jenkins , Barry Linder
IPC分类号： G06F1/3206 , G01R31/28 , G01R19/00 , G06F1/3296 , G06F1/3237
摘要： Over at least part of a lifetime of a product circuit, quiescent current to a product circuit is periodically measured. Over the part of the lifetime of the product circuit, voltage to the product circuit is periodically adjusted based on the monitored quiescent current. Methods, apparatus, and computer program product are disclosed. A calibration procedure may also be performed as part of manufacturing the product circuit, in order to provide values for the quiescent current and corresponding voltage to which the voltage should be adjusted.

14. 发明申请

US20170254846A1 ON-CHIP LEAKAGE MEASUREMENT 有权
公开(公告)号：US20170254846A1
公开(公告)日：2017-09-07
申请号：US15060497
申请日：2016-03-03
申请人： International Business Machines Corporation
发明人： Chen-Yong Cher , Keith A. Jenkins , Barry P. Linder
IPC分类号： G01R31/02 , G01R19/165
CPC分类号： G01R31/025 , G01R19/165 , G01R31/2884 , G01R31/3008
摘要： Method of measuring semiconductor device leakage which includes: providing a semiconductor device powered by a supply voltage and having a circuit block of transistors; providing on the semiconductor device a test circuit providing an input to a counter and a fixed-frequency measurement clock to provide a clock signal to the counter; disconnecting a system clock from the circuit block; receiving by the test circuit the supply voltage as an input; initializing the counter; starting the counter when the supply voltage is at or below a first voltage Vhigh; monitoring a decrease of the supply voltage with time; stopping the counter when the supply voltage is at or below a second voltage Vlow such that Vhigh is greater than Vlow; and reading the counter to provide the semiconductor device leakage metric. Also disclosed is an apparatus and a computer program product.

15. 发明授权

US09594558B2 Silent store detection and recording in memory storage 有权
标题翻译：在存储器中静音存储检测和记录
公开(公告)号：US09594558B2
公开(公告)日：2017-03-14
申请号：US15245946
申请日：2016-08-24
申请人： International Business Machines Corporation
发明人： Pradip Bose , Chen-Yong Cher , Ravi Nair
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3863 , G06F11/00 , G06F11/30
摘要： An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.
摘要翻译：一方面包括接收包括存储器地址和写数据的写请求。从存储器地址的存储器位置读取存储的数据。基于确定存储器位置未被修改，将存储的数据与写入数据进行比较。基于与写入数据匹配的存储数据，完成写入请求而不将写入数据写入存储器，并且设置无声存储位图中的相应静默存储位。基于与写入数据不匹配的存储数据，将写入数据写入存储器位置，无声存储位被复位并且相应的修改位被置位。为应用程序和操作系统中的至少一个提供对静默存储位图的访问。

16. 发明授权

US09417882B2 Load synchronization with streaming thread cohorts 有权
标题翻译：加载与线程队列同步
公开(公告)号：US09417882B2
公开(公告)日：2016-08-16
申请号：US14138724
申请日：2013-12-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jose R. Brunheroto , Chen-Yong Cher , Hubertus Franke , Jamin Naghmouchi
IPC分类号： G06F7/00 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/30043 , G06F9/3824 , G06F9/383 , G06F9/3887
摘要： There is provided a processor implemented method for controlling a lock-stepped cohort. The method includes receiving instructions for each of a first lane and a second lane. The first lane is for the lock-stepped cohort and the second lane is for another cohort. The method further includes detecting a condition in which a first instruction at the first lane will have a higher latency than a second instruction at the second lane. The method also includes setting an indicator indicating where the first lane encountered the first instruction. The method additionally includes setting the first lane to inactive, while keeping the second lane active. The method further includes setting the first lane to active on a subsequent opportunity to execute said first instruction.
摘要翻译：提供了一种用于控制锁步队列的处理器实现方法。该方法包括接收第一通道和第二通道中的每一个的指令。第一条车道是锁定阶段的队列，第二条车道是另一个队列。该方法还包括检测第一通道的第一指令在第二通道处具有比第二指令更高的延迟的状况。该方法还包括设置指示第一车道遇到第一指令的位置的指示符。该方法另外包括将第一车道设置为无效，同时保持第二车道活动。所述方法还包括将所述第一通道设置为在随后的机会中激活以执行所述第一指令。

17. 发明申请

US20160103736A1 PROCESSOR REGISTER ERROR CORRECTION MANAGEMENT 有权
标题翻译：处理器寄存器错误修正管理
公开(公告)号：US20160103736A1
公开(公告)日：2016-04-14
申请号：US14510350
申请日：2014-10-09
申请人： International Business Machines Corporation
发明人： Pradip Bose , Chen-Yong Cher , Meeta S. Gupta
IPC分类号： G06F11/10 , G06F11/07
CPC分类号： G06F11/073 , G06F11/0721 , G06F11/0793 , G06F11/1666 , G06F11/20
摘要： Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.
摘要翻译：公开了处理器寄存器保护管理。在实施例中，处理器寄存器保护管理的方法可以包括确定由编译器产生的可执行代码的敏感逻辑寄存器，产生识别敏感逻辑寄存器的纠错表，以及将错误校正表存储在由处理器。处理器可以被配置为生成由纠错表识别的敏感逻辑寄存器的重复寄存器。

18. 发明申请

US20160085640A1 METHODS, APPARATUS AND SYSTEM FOR SELECTIVE DUPLICATION OF SUBTASKS 审中-公开
公开(公告)号：US20160085640A1
公开(公告)日：2016-03-24
申请号：US14957584
申请日：2015-12-02
申请人： International Business Machines Corporation
发明人： Carlos H. Andrade Costa , Chen-Yong Cher , Yoonho Park , Bryan S. Rosenburg , Kyung D. Ryu
IPC分类号： G06F11/14 , G06F11/34 , G06F11/30
CPC分类号： G06F11/1415 , G06F11/008 , G06F11/0754 , G06F11/1482 , G06F11/1492 , G06F11/2023 , G06F11/203 , G06F11/2048 , G06F11/302 , G06F11/3409 , H04L67/1034
摘要： A method for selective duplication of subtasks in a high-performance computing system includes: monitoring a health status of one or more nodes in a high-performance computing system, where one or more subtasks of a parallel task execute on the one or more nodes; identifying one or more nodes as having a likelihood of failure which exceeds a first prescribed threshold; selectively duplicating the one or more subtasks that execute on the one or more nodes having a likelihood of failure which exceeds the first prescribed threshold; and notifying a messaging library that one or more subtasks were duplicated.

19. 发明授权

US09280383B2 Checkpointing for a hybrid computing node 有权
标题翻译：检查点混合计算节点
公开(公告)号：US09280383B2
公开(公告)日：2016-03-08
申请号：US14302921
申请日：2014-06-12
申请人： International Business Machines Corporation
发明人： Chen-Yong Cher
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4818 , G06F9/461 , G06F9/4881 , G06F11/1438 , G06F11/202
摘要： According to an aspect, a method for checkpointing in a hybrid computing node includes executing a task in a processing accelerator of the hybrid computing node. A checkpoint is created in a local memory of the processing accelerator. The checkpoint includes state data to restart execution of the task in the processing accelerator upon a restart operation. Execution of the task is resumed in the processing accelerator after creating the checkpoint. The state data of the checkpoint are transferred from the processing accelerator to a main processor of the hybrid computing node while the processing accelerator is executing the task.
摘要翻译：根据一方面，一种用于在混合计算节点中进行检查点的方法包括在所述混合计算节点的处理加速器中执行任务。在处理加速器的本地存储器中创建一个检查点。检查点包括在重新启动操作时重新执行处理加速器中的任务的状态数据。创建检查点后，在处理加速器中恢复执行任务。当处理加速器执行任务时，检查点的状态数据从处理加速器传送到混合计算节点的主处理器。

20. 发明申请

US20150268856A1 MANAGING HIGH PERFORMANCE STORAGE SYSTEMS WITH HYBRID STORAGE TECHNOLOGIES 审中-公开
标题翻译：用混合存储技术管理高性能存储系统
公开(公告)号：US20150268856A1
公开(公告)日：2015-09-24
申请号：US14220471
申请日：2014-03-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Chen-Yong Cher , Michele M. Franceschini , Ashish Jagmohan
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F3/061 , G06F3/0634 , G06F3/0653 , G06F3/0685 , G06F11/3034 , G06F11/3433 , G06F11/3485 , G06F12/0246 , G06F2212/1041 , G06F2212/7205 , G06F2212/7208 , G06F2212/7211 , G11C16/349 , G11C2029/0409
摘要： There is provided a method for managing a solid state storage system with hybrid storage technologies. The method includes monitoring one or more storage request streams to identify operating mode characteristics therein from among a set of possible operating mode characteristics. The set of possible operating mode characteristics correspond to a set of available operating modes of the hybrid storage technologies. The method further includes identifying a current operating mode from among the set of available operating modes responsive to the identified operating mode characteristics. The method also includes predicting a likely future operating mode responsive to variations in workload requirements to generate at least one future operating mode prediction. The method additionally includes controlling at least one of data placement, wear leveling, and garbage collection, responsive to the at least one future operating mode prediction.
摘要翻译：提供了一种使用混合存储技术管理固态存储系统的方法。该方法包括从一组可能的操作模式特性中监视一个或多个存储请求流以识别其中的操作模式特性。可能的操作模式特征的集合对应于混合存储技术的一组可用操作模式。所述方法还包括响应于所识别的操作模式特性，从所述一组可用操作模式中识别当前操作模式。该方法还包括响应于工作负载需求的变化来预测可能的未来操作模式以生成至少一个未来的操作模式预测。该方法还包括响应于至少一个未来的操作模式预测来控制数据放置，磨损均衡和垃圾收集中的至少一个。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式