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11. 发明申请

US20170364133A1 Method, Apparatus, And System For Energy Efficiency And Energy Conservation Including Power And Performance Balancing Between Multiple Processing Elements And/Or A Communication Bus 审中-公开
公开(公告)号：US20170364133A1
公开(公告)日：2017-12-21
申请号：US15611876
申请日：2017-06-02
申请人： Intel Corporation
发明人： Travis T. Schluessler , Russell J. Fenger
IPC分类号： G06F1/32 , G06F1/20 , G06F9/50
CPC分类号： G06F1/3206 , G06F1/206 , G06F1/3203 , G06F1/3253 , G06F1/3287 , G06F1/329 , G06F9/50 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

12. 发明授权

US09703352B2 Method, apparatus, and system for energy efficiency and energy conservation including power and performance balancing between multiple processing elements and/or a communication bus 有权
公开(公告)号：US09703352B2
公开(公告)日：2017-07-11
申请号：US14526040
申请日：2014-10-28
申请人： Intel Corporation
发明人： Travis T. Schluessler , Russell J. Fenger
IPC分类号： G06F1/32 , G06F1/20 , G06F9/50
CPC分类号： G06F1/3206 , G06F1/206 , G06F1/3203 , G06F1/3253 , G06F1/3287 , G06F1/329 , G06F9/50 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

13. 发明申请

US20160371118A1 VIRTUAL MACHINE MANAGEMENT METHOD AND APPARATUS INCLUDING IDLING AND SCHEDULING OF VIRTUAL PROCESSORS 审中-公开
标题翻译：虚拟机管理方法和设备，包括虚拟处理器的定位和调度
公开(公告)号：US20160371118A1
公开(公告)日：2016-12-22
申请号：US14741782
申请日：2015-06-17
申请人： Intel Corporation
发明人： Vijay Dhanraj , Abhinav R. Karhu , Gaurav Khanna , Russell J. Fenger
IPC分类号： G06F9/50 , G06F9/455
CPC分类号： G06F9/485 , G06F9/45558 , G06F9/5027 , G06F9/5077 , G06F2009/4557 , G06F2009/45575
摘要： Apparatuses, methods and storage media associated with managing operations of a virtual machine including dynamic idling and scheduling of virtual processors on logical processors described herein. In embodiments, an apparatus may include a physical computing platform with one or more physical processors, a virtual machine manager to manage operation of virtual machines each with a priority level and with one or more virtual processors that operate on logical processor instances of the one or more physical processors, wherein the virtual machine manager tracks activities of the virtual processors that operate on a shared logical processor instance and selectively idles and schedules one or more virtual processors in view of at least the activities of the virtual processors that operate on a shared logical processor instance and the priority of the virtual machines associated with the one or more virtual processors.
摘要翻译：与管理虚拟机的操作相关联的装置，方法和存储介质，包括本文所述的逻辑处理器上的虚拟处理器的动态空闲和调度。在实施例中，装置可以包括具有一个或多个物理处理器的物理计算平台，虚拟机管理器，用于管理各自具有优先级的虚拟机的操作，以及一个或多个虚拟处理器，其在一个或多个物理处理器的逻辑处理器实例上操作更多物理处理器，其中虚拟机管理器跟踪在共享逻辑处理器实例上操作的虚拟处理器的活动，并且考虑到至少在共享逻辑上操作的虚拟处理器的活动，选择性地空闲并调度一个或多个虚拟处理器处理器实例和与一个或多个虚拟处理器相关联的虚拟机的优先级。

14. 发明授权

US08683240B2 Increasing power efficiency of turbo mode operation in a processor 有权
标题翻译：在处理器中提高涡轮模式运行的功率效率
公开(公告)号：US08683240B2
公开(公告)日：2014-03-25
申请号：US13780038
申请日：2013-02-28
申请人： Intel Corporation
发明人： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, Jr. , Suresh Sugumar
IPC分类号： G06F1/00 , G06F9/46
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/329 , G06F9/5094 , Y02D10/22 , Y02D10/24
摘要： In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器具有多个核来执行线程。处理器还包括功率控制逻辑，用于基于存储核心功率计数的计数器的阈值和识别至少一个线程的turbo模式请求的性能组合之间的比较来进入turbo模式。以这种方式，可以在提供高功率效率的处理器的利用水平上输入turbo模式。描述和要求保护其他实施例。

15. 发明公开

US20240103914A1 DYNAMICALLY ADJUSTING THREAD AFFINITIZATION USING HARDWARE-BASED CORE AVAILABILITY NOTIFICATIONS 审中-公开
公开(公告)号：US20240103914A1
公开(公告)日：2024-03-28
申请号：US17954411
申请日：2022-09-28
申请人： Intel Corporation
发明人： Russell J. Fenger , Rajshree A. Chabukswar , Benjamin Graniello , Monica Gupta , Guy M. Therien , Michael W. Chynoweth
IPC分类号： G06F9/48 , G06F1/3228
CPC分类号： G06F9/4887 , G06F1/3228
摘要： In one embodiment, a processor includes: a plurality of cores to execute instructions; at least one monitor coupled to the plurality of cores to measure at least one of power information, temperature information, or scalability information; and a control circuit coupled to the at least one monitor. Based at least in part on the at least one of the power information, the temperature information, or the scalability information, the control circuit is to notify an operating system that one or more of the plurality of cores are to transition to a forced idle state in which non-affinitized workloads are prevented from being scheduled. Other embodiments are described and claimed.

16. 发明授权

US11354213B2 Utilization metrics for processing engines 有权
公开(公告)号：US11354213B2
公开(公告)日：2022-06-07
申请号：US16647563
申请日：2018-08-27
申请人： Intel Corporation
发明人： Hisham Abu Salah , Arthur Leonard Brown , Russell J. Fenger , Deepak Samuel Kirubakaran , Asit K. Mallick , Jun Pan , Srinivas Pandruvada , Efraim Rotem , Arjan Van De Ven , Eliezer Weissmann , Rafal J. Wysocki
IPC分类号： G06F9/46 , G06F11/34 , G06F11/30 , G06F9/48 , G06F9/50
摘要： In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

17. 发明申请

US20210294641A1 DYNAMIC INTERRUPT STEERING AND PROCESSOR UNIT IDLE STATE DEMOTION 有权
公开(公告)号：US20210294641A1
公开(公告)日：2021-09-23
申请号：US17342476
申请日：2021-06-08
申请人： Intel Corporation
发明人： Deepak Samuel Kirubakaran , William A. Braun , Rajshree A. Chabukswar , Leigh Davies , Russell J. Fenger , Alexander Gendler , Raoul V. Rivas Toledano , Eliezer Weissmann
IPC分类号： G06F9/48 , G06F11/30 , G06F11/34
摘要： Dynamic interrupt steering remaps the handling of interrupts away from processor units executing important workloads. During the operation of a computing system, important workload utilization rates for processor units handling interrupts are determined and those processor units with utilization rates about a threshold value are made unavailable for handling interrupts. Interrupts are dynamically remapped to processor units available for interrupt handling based on processor unit idle state and, in the case of heterogeneous computing systems, processor unit type. Processor units are capable of idle state demotion by, in response to receiving a request to enter into a deep idle state, determining if its interrupt handling rate is greater than a threshold value, and if so, placing itself into a shallower idle state than requested. This avoids the computing system from incurring the expensive idle state exit latency and power costs associated with exiting from a deep idle state.

18. 发明申请

US20200272513A1 Thread Scheduling Using Processing Engine Information 审中-公开
公开(公告)号：US20200272513A1
公开(公告)日：2020-08-27
申请号：US16740794
申请日：2020-01-13
申请人： Intel Corporation
发明人： Avinash N. Ananthakrishnan , Vijay Dhanraj , Russell J. Fenger , Vivek Garg , Eugene Gorbatov , Stephen H. Gunther , Monica Gupta , Efraim Rotem , Krishnakanth V. Sistla , Guy M. Therien , Ankush Varma , Eliezer Weissmann
IPC分类号： G06F9/48 , G06F9/30
摘要： In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

19. 发明申请

US20190102274A1 Utilization Metrics for Processing Engines 审中-公开
公开(公告)号：US20190102274A1
公开(公告)日：2019-04-04
申请号：US15720585
申请日：2017-09-29
申请人： Intel Corporation
发明人： Hisham Abu Salah , Arthur Leonard Brown , Russell J. Fenger , Deepak Samuel Kirubakaran , Asit K. Mallick , Jacob Jun Pan , Srinivas Pandruvada , Efraim Rotem , Arjan Van De Ven , Eliezer Weissmann , Rafal J. Wysocki
IPC分类号： G06F11/34 , G06F9/48 , G06F9/50
摘要： In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

20. 发明申请

US20180365022A1 DYNAMIC OFFLINING AND ONLINING OF PROCESSOR CORES 审中-公开
公开(公告)号：US20180365022A1
公开(公告)日：2018-12-20
申请号：US15625423
申请日：2017-06-16
申请人： Intel Corporation
发明人： Ankush Varma , Nikhil Gupta , Krishnakanth V. Sistla , Corey D. Gough , Vasudevan Srinivasan , Eliezer Weissmann , Stephen H. Gunther , Eugene Gorbatov , Russell J. Fenger , Guy M. Therien
IPC分类号： G06F9/44 , G06F3/06
摘要： Embodiments of processors, methods, and systems for dynamic offlining and onlining of processor cores are described. In an embodiment, a processor includes a plurality of cores, a core status storage location, and a core tracker. Core status information for at least one of the plurality of cores is the be stored in the core status storage location. The core status information is to include a core state to be used by a software scheduler. The core state is to be one of a plurality of core state values including an online value, a requesting-to-go-offline value, and an offline value. The core tracker is to track usage of the at least one core and to change the core state from the online value to the requesting-to-go-offline value in response to determining that usage has reached a predetermined threshold.

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