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11. 发明授权

US08566760B2 Method and apparatus for multi-die thermal analysis 有权
标题翻译：多模热分析的方法和装置
公开(公告)号：US08566760B2
公开(公告)日：2013-10-22
申请号：US13477005
申请日：2012-05-21
申请人： Eddy Pramono , Yong Zhan , Vinod Kariat
发明人： Eddy Pramono , Yong Zhan , Vinod Kariat
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.
摘要翻译：本发明的一些实施例提供了一种用于执行多管芯集成电路（IC）设计布局的热分析的方法。热分析产生温度分布，用于分析多管芯设计中每个管芯的内部特性，并根据两个或多个管芯的内部结构分析设计的两个或多个管芯之间的热相互作用。因此，在一些实施例中，温度分布示出了每个管芯的温度分布，并且各个温度分布在每个管芯上显示变化的温度。一些实施例通过基于引入的两个管芯之间的边界处的热效应引入的导热段构建高质量预处理器来减少执行热分析所需的迭代次数。

12. 发明申请

US20120304137A1 METHOD AND APPARATUS FOR MULTI-DIE THERMAL ANALYSIS 有权
标题翻译：多模热分析方法与装置
公开(公告)号：US20120304137A1
公开(公告)日：2012-11-29
申请号：US13477005
申请日：2012-05-21
申请人： Eddy Pramono , Yong Zhan , Vinod Kariat
发明人： Eddy Pramono , Yong Zhan , Vinod Kariat
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.
摘要翻译：本发明的一些实施例提供了一种用于执行多管芯集成电路（IC）设计布局的热分析的方法。热分析产生温度分布，用于分析多管芯设计中每个管芯的内部特性，并根据两个或多个管芯的内部结构分析设计的两个或多个管芯之间的热相互作用。因此，在一些实施例中，温度分布示出了每个管芯的温度分布，并且各个温度分布在每个管芯上显示变化的温度。一些实施例通过基于引入的两个管芯之间的边界处的热效应引入的导热段构建高质量预处理器来减少执行热分析所需的迭代次数。

13. 发明授权

US06836873B1 Static noise analysis with noise window estimation and propagation 有权
标题翻译：噪声窗口估计和传播的静态噪声分析
公开(公告)号：US06836873B1
公开(公告)日：2004-12-28
申请号：US10313857
申请日：2002-12-06
申请人： Kenneth Tseng , Vinod Kariat
发明人： Kenneth Tseng , Vinod Kariat
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： Static noise analysis simulates crosstalk functional noise by estimating a crosstalk functional noise window and by calculating the propagation of the noise window through a network. For example, the analysis can include simulations of injecting a noise window onto a network, propagating the noise window through the network until it reaches a register, and comparing the noise window with a register's sensitive window. The noise window for the net is calculated based on a duration of time in which noise glitches caused by capacitive coupling to aggressor nets can occur. The noise window is propagated through the net in a forward direction until the noise is attenuated or reaches a register's input. At the register's input, a sensitive window can filter the noise window so that only the portion of the noise window that coincides with the register's clock trigger time is considered in the noise analysis.
摘要翻译：静态噪声分析通过估计串扰功能噪声窗口和通过网络计算噪声窗口的传播来模拟串扰功能噪声。例如，分析可以包括将噪声窗口注入到网络上的模拟，通过网络传播噪声窗口，直到其到达寄存器，并将噪声窗口与寄存器的敏感窗口进行比较。基于由电容耦合引起的噪声毛刺可能发生的时间持续时间来计算网络的噪声窗口。噪声窗口通过网络向前传播，直到噪声衰减或达到寄存器的输入。在寄存器的输入端，敏感窗口可以对噪声窗口进行滤波，从而在噪声分析中只考虑噪声窗口与寄存器时钟触发时间一致的部分。

14. 发明申请

US20120210285A1 METHOD AND APPARATUS FOR THERMAL ANALYSIS OF THROUGH-SILICON VIA (TSV) 有权
标题翻译：通过硅（TSV）热分析的方法和装置
公开(公告)号：US20120210285A1
公开(公告)日：2012-08-16
申请号：US13290047
申请日：2011-11-04
申请人： Vinod Kariat , Eddy Pramono , Yong Zhan
发明人： Vinod Kariat , Eddy Pramono , Yong Zhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F17/5036 , G06F2217/10 , G06F2217/78 , G06F2217/80
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.
摘要翻译：本发明的一些实施例提供了一种用于执行集成电路（“IC”）设计布局的热分析的方法。在一些实施例中，IC设计布局包括若干布线层。 IC设计布局包括具有至少一个穿硅通孔（“TSV”）的基板。该方法将IC设计布局分为一组元素。该方法通过使用一组元素来识别IC设计布局的温度分布。在一些实施方案中，至少一种元素包括金属组分和非金属组分。在一些实施方案中，非金属组分为硅，在其它实施方案中为非电介质。

15. 发明申请

US20100023903A1 METHOD AND APPARATUS FOR MULTI-DIE THERMAL ANALYSIS 有权
标题翻译：多模热分析方法与装置
公开(公告)号：US20100023903A1
公开(公告)日：2010-01-28
申请号：US12180490
申请日：2008-07-25
申请人： Eddy Pramono , Yong Zhan , Vinod Kariat
发明人： Eddy Pramono , Yong Zhan , Vinod Kariat
IPC分类号： G06F9/45
CPC分类号： G06F17/5036
摘要： Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distribution show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.
摘要翻译：本发明的一些实施例提供了一种用于执行多管芯集成电路（IC）设计布局的热分析的方法。热分析产生温度分布，用于分析多管芯设计中每个管芯的内部特性，并根据两个或多个管芯的内部结构分析设计的两个或多个管芯之间的热相互作用。因此，在一些实施例中，温度分布示出了每个管芯的温度分布，并且各个温度分布显示出每个管芯的温度变化。一些实施例通过基于引入的两个管芯之间的边界处的热效应引入的导热段构建高质量预处理器来减少执行热分析所需的迭代次数。

16. 发明申请

US20090319965A1 METHOD AND APPARATUS FOR THERMAL ANALYSIS OF THROUGH-SILICON VIA (TSV) 有权
标题翻译：通过硅（TSV）热分析的方法和装置
公开(公告)号：US20090319965A1
公开(公告)日：2009-12-24
申请号：US12416793
申请日：2009-04-01
申请人： Vinod Kariat , Eddy Pramono , Yong Zhan
发明人： Vinod Kariat , Eddy Pramono , Yong Zhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F17/5036 , G06F2217/10 , G06F2217/78 , G06F2217/80
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.
摘要翻译：本发明的一些实施例提供了一种用于执行集成电路（“IC”）设计布局的热分析的方法。在一些实施例中，IC设计布局包括若干布线层。 IC设计布局包括具有至少一个穿硅通孔（“TSV”）的基板。该方法将IC设计布局分为一组元素。该方法通过使用一组元素来识别IC设计布局的温度分布。在一些实施方案中，至少一种元素包括金属组分和非金属组分。在一些实施方案中，非金属组分为硅，在其它实施方案中为非电介质。

17. 发明授权

US08543952B2 Method and apparatus for thermal analysis of through-silicon via (TSV) 有权
标题翻译：通硅（TSV）热分析方法及装置
公开(公告)号：US08543952B2
公开(公告)日：2013-09-24
申请号：US13290047
申请日：2011-11-04
申请人： Vinod Kariat , Eddy Pramono , Yong Zhan
发明人： Vinod Kariat , Eddy Pramono , Yong Zhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F17/5036 , G06F2217/10 , G06F2217/78 , G06F2217/80
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.
摘要翻译：本发明的一些实施例提供了一种用于执行集成电路（“IC”）设计布局的热分析的方法。在一些实施例中，IC设计布局包括若干布线层。 IC设计布局包括具有至少一个穿硅通孔（“TSV”）的基板。该方法将IC设计布局分为一组元素。该方法通过使用一组元素来识别IC设计布局的温度分布。在一些实施方案中，至少一种元素包括金属组分和非金属组分。在一些实施方案中，非金属组分为硅，在其它实施方案中为非电介质。

18. 发明授权

US07900166B2 Method to produce an electrical model of an integrated circuit substrate and related system and article of manufacture 有权
标题翻译：制造集成电路基板及相关系统及制品的电气模型的方法
公开(公告)号：US07900166B2
公开(公告)日：2011-03-01
申请号：US11769675
申请日：2007-06-27
申请人： Vinod Kariat , Xiaopeng Dong , David Noice
发明人： Vinod Kariat , Xiaopeng Dong , David Noice
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5036
摘要： A method is provided to produce a model of an integrated circuit substrate, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; and connecting the mapped tile instances to each other to produce a tile grid that models overall electrical behavior of the substrate.
摘要翻译：提供了一种用于产生集成电路基板的模型的方法，所述方法包括：提供指定与所述瓦片的实例相关联的电模型的瓦片定义; 将多个相应的瓦片实例映射到所述基板的相应位置; 以及将映射的瓦片实例彼此连接以产生对基板的整体电气行为进行建模的瓦格网格。

19. 发明申请

US20090319964A1 METHOD AND APPARATUS FOR THERMAL ANALYSIS 有权
标题翻译：用于热分析的方法和装置
公开(公告)号：US20090319964A1
公开(公告)日：2009-12-24
申请号：US12144651
申请日：2008-06-24
申请人： Vinod Kariat , Eddy Pramono , Yong Zhan
发明人： Vinod Kariat , Eddy Pramono , Yong Zhan
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/16
摘要： Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element includes several wires. The method computes a set of conductivity groups of values for the set of elements. The method identifies a temperature distribution for the IC design layout based on the set of conductivity groups of values. In some embodiments, each of these elements corresponds to a particular portion of a particular layer of the IC design layout. Each element includes several nodes. Each conductivity group of values is defined by entry values. Each entry value describes how heat flow at a particular node of the element is affected by a temperature change at another particular node of the element.
摘要翻译：本发明的一些实施例提供了一种用于执行包括许多电路模块的集成电路（“IC”）设计布局的热分析的方法。该方法将IC设计布局分为一组元素，其中至少一个元素包含多个线。该方法计算一组元素的一组电导率值。该方法基于一组导电率值来识别IC设计布局的温度分布。在一些实施例中，这些元件中的每一个对应于IC设计布局的特定层的特定部分。每个元素包括几个节点。每个电导率值的值由入口值定义。每个入口值描述了元件的特定节点处的热流如何受到该元件的另一特定节点处的温度变化的影响。

20. 发明授权

US08694934B2 Method and apparatus for multi-die thermal analysis 有权
标题翻译：多模热分析的方法和装置
公开(公告)号：US08694934B2
公开(公告)日：2014-04-08
申请号：US13477006
申请日：2012-05-21
申请人： Eddy Pramono , Yong Zhan , Vinod Kariat
发明人： Eddy Pramono , Yong Zhan , Vinod Kariat
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.
摘要翻译：本发明的一些实施例提供了一种用于执行多管芯集成电路（IC）设计布局的热分析的方法。热分析产生温度分布，用于分析多管芯设计中每个管芯的内部特性，并根据两个或多个管芯的内部结构分析设计的两个或多个管芯之间的热相互作用。因此，在一些实施例中，温度分布示出了每个管芯的温度分布，并且各个温度分布在每个管芯上显示变化的温度。一些实施例通过基于引入的两个管芯之间的边界处的热效应引入的导热段构建高质量预处理器来减少执行热分析所需的迭代次数。

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