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    • 11. 发明申请
    • Etching structure
    • 蚀刻结构
    • US20080241469A1
    • 2008-10-02
    • US12153867
    • 2008-05-27
    • Katsuaki KaifuJuro Mita
    • Katsuaki KaifuJuro Mita
    • B32B7/00
    • H01L21/31116H01L21/7688Y10T428/24174
    • An etching structure includes a substrate, a to be etched filmcovering the principal surface of the substrate, and an exposure region exposing the principal surface of the substrate and obtained by removing a part of the to be etched film. A region of the to be etched film constitutes a peripheral region surrounding the exposure region. Another region of the to be etched film outside the peripheral region constitutes a flat region. The film thickness of the to be etched film increases as the distance from the exposure region increases, such that the inclination of the outline of the cross section of the to be etched film that exists within the peripheral region decreases as the distance from the exposure region increases. The to be etched film has a side wall that extends perpendicularly to the principal surface at a boundary between the peripheral region and the flat region.
    • 蚀刻结构包括:衬底,待蚀刻的膜覆盖衬底的主表面;以及暴露区域,暴露衬底的主表面并通过去除被蚀刻膜的一部分而获得。 被蚀刻膜的区域构成围绕曝光区域的周边区域。 要在周边区域外的被蚀刻膜的另一区域构成平坦区域。 被蚀刻膜的膜厚随着与曝光区域的距离增大而增加,使得存在于周边区域内的被蚀刻膜的截面的轮廓的倾斜度随着与曝光区域的距离而减小 增加 要被蚀刻的膜具有在周边区域和平坦区域之间的边界处垂直于主表面延伸的侧壁。
    • 14. 发明授权
    • Method of manufacturing field effect transistor having Ohmic electrode in a recess
    • 在凹槽中制造具有欧姆电极的场效应晶体管的方法
    • US08202794B2
    • 2012-06-19
    • US13064637
    • 2011-04-05
    • Juro MitaKatsuaki Kaifu
    • Juro MitaKatsuaki Kaifu
    • H01L21/28H01L21/3205H01L21/44H01L29/06H01L31/00H01L29/66
    • H01L29/452H01L29/2003H01L29/41725H01L29/7783
    • The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.
    • 与将欧姆电极提供到比异质界面更深的情况相比,欧姆电极和电子转移层之间的接触电阻降低。 结果,对于在由形成在基板上的第一半导体层形成的电子转移层的结构中提供的欧姆电极,包括与电子转移层形成异质结并具有较小电子的第二半导体层的电子供给层 亲和性比第一半导体层和在异质界面附近的电子转移层中感应的二维电子层,欧姆电极的端部位于电子转移层中,在电子转移层中以 深度等于或大于异质界面。
    • 15. 发明授权
    • Field effect transistor having Ohmic electrode in a recess
    • 在凹槽中具有欧姆电极的场效应晶体管
    • US07923753B2
    • 2011-04-12
    • US11505301
    • 2006-08-17
    • Juro MitaKatsuaki Kaifu
    • Juro MitaKatsuaki Kaifu
    • H01L29/66H01L29/06H01L21/28H01L21/44
    • H01L29/452H01L29/2003H01L29/41725H01L29/7783
    • The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.
    • 与将欧姆电极提供到比异质界面更深的情况相比,欧姆电极和电子转移层之间的接触电阻降低。 结果,对于在由形成在基板上的第一半导体层形成的电子转移层的结构中提供的欧姆电极,包括与电子转移层形成异质结并具有较小电子的第二半导体层的电子供给层 亲和性比第一半导体层和在异质界面附近的电子转移层中感应的二维电子层,欧姆电极的端部位于电子转移层中,在电子转移层中以 深度等于或大于异质界面。
    • 18. 发明申请
    • Method of manufacturing field effect transistor having Ohmic electrode in a recess
    • 在凹槽中制造具有欧姆电极的场效应晶体管的方法
    • US20110189826A1
    • 2011-08-04
    • US13064637
    • 2011-04-05
    • Juro MitaKatsuaki Kaifu
    • Juro MitaKatsuaki Kaifu
    • H01L21/338
    • H01L29/452H01L29/2003H01L29/41725H01L29/7783
    • The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.
    • 与将欧姆电极提供到比异质界面更深的情况相比,欧姆电极和电子转移层之间的接触电阻降低。 结果,对于在由形成在基板上的第一半导体层形成的电子转移层的结构中提供的欧姆电极,包括与电子转移层形成异质结并具有较小电子的第二半导体层的电子供给层 亲和性比第一半导体层和在异质界面附近的电子转移层中感应的二维电子层,欧姆电极的端部位于电子转移层中,在电子转移层中以 深度等于或大于异质界面。
    • 19. 发明申请
    • Etching method, method of fabricating metal film structure, and etching structure
    • 蚀刻方法,金属膜结构的制造方法和蚀刻结构
    • US20070049031A1
    • 2007-03-01
    • US11512341
    • 2006-08-30
    • Katsuaki KaifuJuro Mita
    • Katsuaki KaifuJuro Mita
    • H01L21/302
    • H01L21/31116H01L21/7688Y10T428/24174
    • There is provided an etching method in which a protective film existing in an etching-destined region of a substrate structure is removed by means of ICP-RIE to form an exposure region of the principal surface of the substrate. The substrate structure comprises a substrate, a protective film formed on the substrate, a photoresist layer formed on the protective film, and a hole formed throughout the photoresist layer. The hole comprises an opening formed in the photoresist layer surface and a hollow linked to the opening in the thickness direction of the photoresist layer and reaching the protective film. ICP-RIE is performed under conditions such that (1) ICP power is 20 to 100 W, (2) RIE power is 5 to 50 W, and (3) the pressure in the etching chamber is 1 to 100 mTorr.
    • 提供一种蚀刻方法,其中通过ICP-RIE去除存在于衬底结构的蚀刻目的地区域中的保护膜,以形成衬底的主表面的曝光区域。 衬底结构包括衬底,形成在衬底上的保护膜,形成在保护膜上的光致抗蚀剂层和在整个光致抗蚀剂层上形成的孔。 孔包括形成在光致抗蚀剂层表面中的开口和在光致抗蚀剂层的厚度方向上连接到开口的中空并到达保护膜。 ICP-RIE在(1)ICP功率为20〜100W的条件下进行,(2)RIE功率为5〜50W,(3)蚀刻室内的压力为1〜100mTorr。