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11. 发明授权

US06732203B2 Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus 有权
标题翻译：选择性地将存储器耦合全局总线数据位复合到较窄的功能单元耦合本地总线
公开(公告)号：US06732203B2
公开(公告)日：2004-05-04
申请号：US10109826
申请日：2002-03-29
申请人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
发明人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
IPC分类号： G06F1338
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30072 , G06F9/30149 , G06F9/30181 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3877 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： In one embodiment, a bus multiplexer is between a memory and a functional unit of the integrated circuit. An input of the bus multiplexer couples to a global bus having a bit width. A local bus having a lesser bit width couples to an output of the bus multiplexer. The bus multiplexer selectively multiplexes bits of data on the global bus onto bits of the local bus. In another embodiment, an integrated circuit comprises a memory, a global bus, and a functional unit coupled together. The functional unit includes a bus multiplexer with an input coupled to the global bus, and a local bus coupled to an output of the bus multiplexer. The bus width of the local bus is less than that of the global bus. The bus multiplexer selects data from a subset of bits of the global bus to couple onto the bits of the local bus.
摘要翻译：在一个实施例中，总线复用器位于集成电路的存储器和功能单元之间。总线多路复用器的输入耦合到具有位宽度的全局总线。具有较小位宽度的本地总线耦合到总线复用器的输出。总线复用器有选择地将全局总线上的数据位复用到本地总线的位上。在另一实施例中，集成电路包括存储器，全局总线和耦合在一起的功能单元。功能单元包括具有耦合到全局总线的输入的总线复用器和耦合到总线多路复用器的输出的本地总线。本地总线的总线宽度小于全球总线的总线宽度。总线复用器从全局总线的位的子集中选择数据以耦合到本地总线的位上。

12. 发明申请

US20150003148A1 Methods and Apparatus for Designing and Constructing Dual Write Memory Circuits with Voltage Assist 有权
标题翻译：用于设计和构造具有电压辅助的双写存储器电路的方法和装置
公开(公告)号：US20150003148A1
公开(公告)日：2015-01-01
申请号：US14274518
申请日：2014-05-09
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C8/16 , G11C11/412 , G11C11/413
摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell. Thus, spatial domain multiplexing with a voltage assist allows single-ended writes to handle two independent write operations to be handled in a single cycle. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.
摘要翻译：在大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据位的表示。为了处理多个并发存储器请求，提出了一种高效的双端口六晶体管（6T）SRAM位单元。双端口6T SRAM单元使用独立的字线和位线，使得可以独立地访问SRAM位单元的真/数据侧和伪/数据补码侧。单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个独立的读操作。通过调整在执行写入时提供给存储单元的VDD电源电压，使得可以使用单个字线和位线对将逻辑“0”或逻辑“1”写入到 SRAM位单元。因此，具有电压辅助的空间域复用允许单端写入来处理在单个周期中处理的两个独立的写操作。可以将写缓冲器添加到存储器系统以防止冲突，从而在单个周期中实现并行读取操作和写入操作。

13. 发明申请

US20140185364A1 Methods And Apparatus For Designing And Constructing Multi-Port Memory Circuits 有权
标题翻译：用于设计和构造多端口存储器电路的方法和装置
公开(公告)号：US20140185364A1
公开(公告)日：2014-07-03
申请号：US13732372
申请日：2013-01-01
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/1006 , G11C7/1051 , G11C7/1075 , G11C7/22 , G11C8/16 , G11C11/412
摘要： Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system.
摘要翻译：大多数数字集成电路中使用静态随机存取存储器（SRAM）电路来存储数据。为了处理多个内存用户，提出了一种高效的双端口六晶体管（6T）SRAM存储单元。双端口6T SRAM单元使用独立的字线和位线，使得可以独立访问SRAM单元的真实面和假面。单端读取允许两个独立的字线和位线使用空间域复用在单个周期中处理两个读取。可以更快地处理写入操作，使得可以使用时分复用在单个周期中处理两个写入操作。为了进一步提高双端口6T SRAM单元的运行，采用了多种算法技术来改善存储系统的运行。

14. 发明授权

US08653325B2 Increased seed size and seed number through transgenic over expression of revoluta protein during early embryo development 失效
标题翻译：通过在早期胚胎发育过程中通过转基因过度表达rotuta蛋白来增加种子大小和种子数量
公开(公告)号：US08653325B2
公开(公告)日：2014-02-18
申请号：US11611832
申请日：2006-12-15
申请人： Jay DeRocher , Thu Nguyen
发明人： Jay DeRocher , Thu Nguyen
IPC分类号： A01H1/00
CPC分类号： C12N15/8234 , C12N15/8261 , Y02A40/146
摘要： The present invention provides methods and compositions for increasing the seed size and/or seed number in plants. In particular, the methods and compositions provide for the over expression of a plant growth and/or development related or associated gene during embryo development. Transgenic plants transformed with genetic constructs having the plant growth and/or development associated gene under the control of an early phase-specific embryo promoter provides mature plants in the field that produce larger and/or more seeds. Methods for selection growth and development associated genes that provide transgenic plants with a higher yield phenotype are also provided.
摘要翻译：本发明提供用于增加植物中种子大小和/或种子数量的方法和组合物。特别地，所述方法和组合物在胚胎发育期间提供植物生长和/或发育相关或相关基因的过度表达。用具有早期阶段特异性胚胎启动子控制下的植物生长和/或发育相关基因的遗传构建体转化的转基因植物提供了在该领域中产生更大和/或更多种子的成熟植物。还提供了提供具有更高产量表型的转基因植物的选择生长和发育相关基因的方法。

15. 发明申请

US20130258757A1 Methods And Apparatus For Synthesizing Multi-Port Memory Circuits 有权
标题翻译：用于合成多端口存储器电路的方法和装置
公开(公告)号：US20130258757A1
公开(公告)日：2013-10-03
申请号：US13434296
申请日：2012-03-29
申请人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
发明人： Sundar Iyer , Shang-Tse Chuang , Thu Nguyen , Sanjeev Joshi , Adam Kablanian
IPC分类号： G11C8/16 , G11C11/00
CPC分类号： G06F17/505 , G06F17/5072 , G11C7/10 , G11C7/1075 , G11C8/16 , G11C11/412 , G11C11/413 , G11C11/419
摘要： Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.
摘要翻译：现代数字集成电路中通常需要多端口存储器电路来存储数据。多端口存储器电路允许多个存储器用户同时访问相同的存储器单元。多端口存储器电路通常是为了获得最佳性能而定制设计的，或者通过用于快速设计的逻辑综合工具来合成。然而，创建多端口存储器的这两个选项为集成电路设计师提供了一个明显的选择：投入大量的时间和金钱来定制设计高效的多端口存储器系统，或允许逻辑综合工具低效地创建多端口存储器。公开了一种中间解决方案，其允许使用标准电路单元组件和寄存器传输级硬件设计语言代码来大量创建有效的多端口存储器阵列。

16. 发明授权

US08464243B2 Updating client node of computing system 失效
标题翻译：更新计算系统的客户端节点
公开(公告)号：US08464243B2
公开(公告)日：2013-06-11
申请号：US12545724
申请日：2009-08-21
申请人： Jean X. Yu , James J. Myers , Gergana V. Markova , Thu Nguyen , David M. Cannon , Kenneth E. Hannigan , James P. Smith , Colin S. Dawson
发明人： Jean X. Yu , James J. Myers , Gergana V. Markova , Thu Nguyen , David M. Cannon , Kenneth E. Hannigan , James P. Smith , Colin S. Dawson
IPC分类号： G06F9/44 , G06F9/445
CPC分类号： G06F8/61
摘要： During execution of an existing scheduling computer program on a client node, an update computer program and a self-describing automatic installation package are downloaded to the client node from a logical depot node implemented on an existing management server. Therefore, advantageously, no physical depot node or other additional computing device is needed for the client node to update itself. Execution of the update computer program is spawned on the client node from the existing scheduling computer program. As such, the update computer program inherits root access to the client node and security credentials to the management server from the scheduling computer program—advantageously, then, a user does not have to perform any laborious configuration of the client node in order to update the node. The client node ultimately updates itself using the self-describing automatic installation package, which includes all the information needed for the client node to update itself.
摘要翻译：在客户机节点上执行现有的调度计算机程序期间，将更新计算机程序和自描述自动安装包从在现有管理服务器上实现的逻辑仓库节点下载到客户端节点。因此，有利的是，客户机节点不需要物理站点节点或其他额外的计算设备来更新自身。从现有的调度计算机程序在客户机节点上产生更新计算机程序的执行。因此，更新计算机程序从调度计算机程序继承对客户端节点的根访问和对管理服务器的安全凭证 - 然后，用户不必执行客户端节点的任何费力配置，以便更新节点。客户端节点最终使用自描述自动安装软件包来自动更新，其中包括客户端节点自身更新所需的所有信息。

17. 发明申请

US20110145950A1 FLORAL DIP METHOD FOR TRANSFORMATION OF CAMELINA 失效
标题翻译：用于转换CAMELINA的花卉DIP方法
公开(公告)号：US20110145950A1
公开(公告)日：2011-06-16
申请号：US12933827
申请日：2009-03-19
申请人： Thu Nguyen , Xunjia Liu , Jay Derocher
发明人： Thu Nguyen , Xunjia Liu , Jay Derocher
IPC分类号： A01H1/00
CPC分类号： C12N15/8205
摘要： The present invention provides methods for transforming Camelina plants. In particular, the present invention relates to transforming Camelina sativa plants through contacting the plants to a dipping solution comprising Agrobacterium, a sugar, and a nonionic surfactant. The methods do not require a vacuum filtration step. The present invention provides, for example, useful methods for developing transformation systems for Camelina sativa that can enable manipulation of its agronomic qualities.
摘要翻译：本发明提供了转化Camelina植物的方法。特别地，本发明涉及通过使植物接触包含农杆菌，糖和非离子表面活性剂的浸渍溶液来转化Camelina sativa植物。该方法不需要真空过滤步骤。本发明提供了例如用于开发Camelina的转化系统的有用方法，其可以操纵其农艺学性质。

18. 发明授权

US07287148B2 Unified shared pipeline allowing deactivation of RISC/DSP units for power saving 有权
标题翻译：统一的共享管道允许停用RISC / DSP单元以节省能耗
公开(公告)号：US07287148B2
公开(公告)日：2007-10-23
申请号：US10651234
申请日：2003-08-28
申请人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
发明人： Ruban Kanapathippillai , Kumar Ganapathy , Thu Nguyen , Siva Venkatraman , Earle F. Philhower, III , Manoj Mehta , Kenneth Malich
IPC分类号： G06F15/16
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/30072 , G06F9/30149 , G06F9/30181 , G06F9/381 , G06F9/382 , G06F9/3853 , G06F9/3877 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and the one or more DSP units, the unified instruction pipeline to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified instruction pipeline to decode and initiate the RISC instructions when the DSP instructions are inactive, and to decode and initiate the DSP instructions when the RISC instructions are inactive.
摘要翻译：一种集成电路，包括执行RISC指令的简化指令集计算机（RISC）控制器，用于执行DSP指令的一个或多个数字信号处理（DSP）单元，以及耦合到所述RISC控制器和所述一个或多个DSP单元的统一指令流水线统一指令流水线，用于解码和启动统一RISC和DSP指令集的RISC指令和DSP指令的执行，当DSP指令不活动时，统一指令流水线解码并启动RISC指令，并解码并启动当RISC指令不活动时，DSP指令。

19. 发明申请

US20070109021A1 Spatial light modulator with four transistor electrode driver 有权
标题翻译：具有四个晶体管电极驱动器的空间光调制器
公开(公告)号：US20070109021A1
公开(公告)日：2007-05-17
申请号：US11282056
申请日：2005-11-16
申请人： Thu Nguyen
发明人： Thu Nguyen
IPC分类号： H03K19/094
CPC分类号： G11C11/412
摘要： A memory cell for driving a complementary pair of electrodes associated with a micro-mirror of a spatial light modulator. The memory cell includes a first PMOS transistor, wherein a source of the first PMOS transistor is coupled to a first supply voltage. The memory cell also includes a first NMOS transistor, wherein a drain of the first NMOS transistor is coupled to a drain of the first PMOS transistor, a source of the first NMOS transistor is coupled to a second supply voltage, and a gate of the first NMOS transistor is coupled to a gate of the first PMOS transistor. The memory cell further includes a second transistor adapted to establish a conduction path between the gate of the first NMOS transistor and at least one of the first supply voltage or the second supply voltage. Moreover, the memory includes a select transistor, wherein a drain of the select transistor is coupled to the gate of the first NMOS transistor and wherein the memory cell is free from a connection to a fifth transistor.
摘要翻译：用于驱动与空间光调制器的微镜相关联的互补电极对的存储单元。存储单元包括第一PMOS晶体管，其中第一PMOS晶体管的源极耦合到第一电源电压。存储单元还包括第一NMOS晶体管，其中第一NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极，第一NMOS晶体管的源极耦合到第二电源电压，第一NMOS晶体管的栅极 NMOS晶体管耦合到第一PMOS晶体管的栅极。存储单元还包括适于在第一NMOS晶体管的栅极与第一电源电压或第二电源电压中的至少一个之间建立导电路径的第二晶体管。此外，存储器包括选择晶体管，其中选择晶体管的漏极耦合到第一NMOS晶体管的栅极，并且其中存储单元没有与第五晶体管的连接。

20. 发明申请

US20070060870A1 Controller device for an infusion pump 审中-公开
标题翻译：输液泵控制装置
公开(公告)号：US20070060870A1
公开(公告)日：2007-03-15
申请号：US11204667
申请日：2005-08-16
申请人： Mike Charles Tolle , Gary Williams , Kaezad Mehta , Linda Torres , Thu Nguyen , Jon Spurlin , Sheldon Moberg
发明人： Mike Charles Tolle , Gary Williams , Kaezad Mehta , Linda Torres , Thu Nguyen , Jon Spurlin , Sheldon Moberg
IPC分类号： A61M31/00
CPC分类号： A61M5/14244 , A61B5/14532 , A61M5/1723 , A61M2205/3553 , A61M2205/3561 , A61M2205/3576 , A61M2205/3584 , A61M2205/3592 , A61M2205/581 , A61M2205/80 , A61M2209/01 , A61M2230/201
摘要： An infusion system that includes a controller device and a communication system to transmit the communications from the controller device to an infusion device pump that controls delivery of fluids to the user's body. More particularly, these apparatuses and methods are for providing convenient monitoring and control of the infusion pump device in determining the appropriate amount of insulin to deliver.
摘要翻译：一种输液系统，其包括控制器装置和通信系统，用于将来自控制器装置的通信传输到控制向使用者身体输送流体的输注装置泵。更具体地，这些装置和方法用于在确定输送胰岛素的适当量时提供对输液泵装置的便利监测和控制。

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