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11. 发明授权

US09754935B2 Raised metal semiconductor alloy for self-aligned middle-of-line contact 有权
公开(公告)号：US09754935B2
公开(公告)日：2017-09-05
申请号：US14453751
申请日：2014-08-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Christian Lavoie , Effendi Leobandung
IPC分类号： H01L27/088 , H01L21/336 , H01L29/78 , H01L21/4763 , H01L29/66 , H01L29/417 , H01L21/768 , H01L29/08 , H01L21/285 , H01L21/8234 , H01L29/165 , H01L23/485 , H01L23/532
CPC分类号： H01L27/088 , H01L21/28518 , H01L21/28525 , H01L21/76897 , H01L21/823425 , H01L23/485 , H01L23/53271 , H01L29/0847 , H01L29/165 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L2924/0002 , H01L2924/00
摘要： A method to form self-aligned middle-of-line (MOL) contacts between functional gate structures without the need of lithographic patterning and etching by using raised metal semiconductor alloy regions is provided. Raised metal semiconductor alloy regions are formed by reacting a metal layer with a semiconductor material in raised semiconductor material regions formed on portions of at least one active region of a substrate located between functional gate structures. The metal layer includes a metal capable of forming a metal semiconductor alloy with a large volume expansion such that the resulting metal semiconductor alloy regions can be raised to a same height as that of the functional gate structures. As a result, no lithographic patterning and etching between functional gate structures are needed when forming MOL contacts to these raised metal semiconductor alloy regions.

12. 发明授权

US09472406B2 Metal semiconductor alloy contact resistance improvement 有权
公开(公告)号：US09472406B2
公开(公告)日：2016-10-18
申请号：US14880429
申请日：2015-10-12
申请人： International Business Machines Corporation
发明人： Emre Alptekin , Nicolas L. Breil , Christian Lavoie , Ahmet S. Ozcan , Kathryn T. Schonenberg
IPC分类号： H01L21/28 , H01L29/45 , H01L29/78 , H01L21/285 , H01L29/66 , H01L23/485 , H01L23/532 , H01L21/768
CPC分类号： H01L21/28026 , H01L21/28512 , H01L21/28518 , H01L21/28568 , H01L21/76843 , H01L21/76855 , H01L21/76858 , H01L23/485 , H01L23/53238 , H01L29/456 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. A first transition metal liner including at least one first transition metal element, a second transition metal liner including at least one second transition metal element that is different from the at least one first transition metal element and a metal contact are sequentially formed within each contact opening. Following a planarization process, the structure is annealed forming metal semiconductor alloy contacts at the bottom of each contact opening. Each metal semiconductor alloy contact that is formed includes the at least one first transition metal element, the at least one second transition metal element and a semiconductor element.

13. 发明授权

US09397283B2 Chip mode isolation and cross-talk reduction through buried metal layers and through-vias 有权
标题翻译：通过掩埋金属层和通孔进行芯片模式隔离和串扰降低
公开(公告)号：US09397283B2
公开(公告)日：2016-07-19
申请号：US14610411
申请日：2015-01-30
申请人： International Business Machines Corporation
发明人： David W. Abraham , George A. Keefe , Christian Lavoie , Mary E. Rothwell
IPC分类号： H01L39/04 , H01L27/18 , H01L39/24 , H01L39/22 , B82Y10/00 , G06N99/00 , H01L23/538
CPC分类号： H01L39/045 , B82Y10/00 , G06N99/002 , H01L23/5384 , H01L27/18 , H01L39/223 , H01L39/2493 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a chip surface base includes preparing a first substrate, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias, preparing a second substrate, bonding the first and second substrates and exposing the metal fillings. A method for fabricating a chip surface base includes preparing a first and second substrate, depositing a metal on at least one of the first and second substrates, bonding the first and second substrates, preparing a plurality of vias in the first substrate, depositing metal fillings into the plurality of vias and exposing the metal fillings. A chip surface base device includes a first substrate, a second substrate, a metal layer disposed between the first and second substrates and a plurality of vias disposed on the first substrate.
摘要翻译：制造芯片表面基底的方法包括制备第一基底，在第一基底中制备多个通孔，将金属填充物沉积到多个通孔中，制备第二基底，粘合第一和第二基底并暴露金属填充物。一种用于制造芯片表面基底的方法，包括制备第一和第二基底，在第一和第二基底中的至少一个上沉积金属，粘合第一和第二基底，在第一基底中制备多个通孔，进入多个通孔并暴露金属填充物。芯片表面基底器件包括第一衬底，第二衬底，设置在第一和第二衬底之间的金属层和设置在第一衬底上的多个通孔。

14. 发明申请

US20160020209A1 FINFET SOURCE-DRAIN MERGED BY SILICIDE-BASED MATERIAL 有权
标题翻译：基于硅化物材料的FINFET源 - 漏极
公开(公告)号：US20160020209A1
公开(公告)日：2016-01-21
申请号：US14561632
申请日：2014-12-05
申请人： International Business Machines Corporation
发明人： Brent A. Anderson , Nicolas Breil , Christian Lavoie
IPC分类号： H01L27/088 , H01L21/285 , H01L21/3213 , H01L29/04 , H01L21/8234 , H01L29/66 , H01L29/45 , H01L29/16 , H01L29/08 , H01L21/324 , H01L29/78
CPC分类号： H01L27/0886 , H01L21/28518 , H01L21/28531 , H01L21/32133 , H01L21/823431 , H01L21/845 , H01L27/1211 , H01L29/0847 , H01L29/165 , H01L29/456 , H01L29/66795 , H01L29/785
摘要： A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a top portion of a silicon cap layer located in direct contact with a first diamond shaped epitaxial layer surrounding a first fin and a second diamond shaped epitaxial layer surrounding a second fin. The metal layer extends from the top portion of the silicon cap layer in direct contact with the first diamond shaped epitaxial layer to the top portion of the silicon cap layer in direct contact with the second diamond shaped epitaxial layer. The conducted laser-based anneal treatment forms a silicide layer, a portion of the silicide layer between the first and the second diamond shaped epitaxial layers is substantially thicker than a portion of the silicide layer in contact with the first and the second diamond shaped epitaxial layers.
摘要翻译：一种方法包括对位于与包围第一鳍片的第一菱形外延层直接接触的硅帽层顶部直接接触的金属层上进行基于激光的退火处理，第二菱形外延围绕第二鳍的层。金属层从第一金刚石外延层的直接接触的硅帽层的顶部延伸到硅帽层的顶部，与第二菱形外延层直接接触。所进行的基于激光的退火处理形成硅化物层，第一和第二菱形外延层之间的硅化物层的一部分基本上比与第一和第二菱形外延层接触的硅化物层的部分厚。

15. 发明申请

US20150325716A1 MANUFACTURE AND STRUCTURE FOR PHOTOVOLTAICS INCLUDING METAL-RICH SILICIDE 审中-公开
标题翻译：包括金属硅酸盐在内的光伏器件的制造和结构
公开(公告)号：US20150325716A1
公开(公告)日：2015-11-12
申请号：US14662989
申请日：2015-03-19
申请人： International Business Machines Corporation
发明人： Brett Caroline Baker-O'Neal , Shu-Yun Chong , John Michael Cotte , Ronald Dean Goldblatt , Jeffrey Hedrick , Qiang Huang , Susan Huang , Laura Louise Kosbar , Hwee Meng Lam , Christian Lavoie , Xiaoyan Shao , Rob Steeman
IPC分类号： H01L31/0224 , H01L31/0216 , H01L31/18
CPC分类号： H01L31/1804 , H01L31/02168 , H01L31/022425 , H01L31/1864 , Y02E10/547 , Y02P70/521
摘要： Photovoltaic devices are formed with electroplated metal grids that are effectively adhered to the devices. Metal-rich silicides, such as nickel silicides, are formed on the devices by annealing. The metal used in the anneal exhibits low stress. Annealing may be conducted in ambient air followed by removal of oxide and excess metal from the metal-rich silicide. Laser patterning of the antireflective coating of the devices can be used to expose the emitter to form front grid contacts. Doping of the emitter in the patterned region can be increased during laser patterning. The ratio of the centerline to centerline pitch per laser width is controlled to ensure sufficient adhesion of subsequently plated busbars.
摘要翻译：光伏器件由电镀金属网格形成，电镀金属网格被有效地粘附到器件上。通过退火在器件上形成富金属硅化物，例如硅化镍。退火中使用的金属显示低应力。可以在环境空气中进行退火，然后从富含金属的硅化物中除去氧化物和过量的金属。可以使用装置的抗反射涂层的激光图案来暴露发射器以形成前栅格触点。激光图案化期间，可以增加图案化区域中的发射极的掺杂。控制中心线与每个激光宽度的中心线间距的比例，以确保随后镀覆的母线的充分粘附。

16. 发明授权

US09093425B1 Self-aligned liner formed on metal semiconductor alloy contacts 有权
标题翻译：自对准衬垫形成在金属半导体合金触点上
公开(公告)号：US09093425B1
公开(公告)日：2015-07-28
申请号：US14177481
申请日：2014-02-11
申请人： International Business Machines Corporation
发明人： Nicolas Breil , Christian Lavoie , Ahmet S. Ozcan , Kathryn T. Schonenberg , Jian Yu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/45 , H01L29/78 , H01L29/16 , H01L29/66 , H01L29/20 , H01L21/285
CPC分类号： H01L29/456 , H01L21/28052 , H01L21/28518 , H01L21/2855 , H01L21/28568 , H01L21/28575 , H01L21/76843 , H01L21/76855 , H01L29/665 , H01L29/66545 , H01L29/78
摘要： Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process.
摘要翻译：金属半导体合金触点设置在存在于半导体基板中的源极区域和漏极区域中的每一个上。然后在每个金属半导体合金触点上沉积过渡金属，并且在沉积过渡金属期间，沉积的过渡金属优选地但不一定总是与形成的每个金属半导体合金触点的一部分原位反应在每个金属半导体合金接触顶上的过渡金属 - 金属半导体合金衬里。设置有过渡金属 - 金属半导体合金衬垫的每个金属半导体合金衬垫的外边缘与每个金属半导体合金触点的外边缘垂直重合。与下面的金属半导体合金相比，过渡金属 - 金属半导体合金衬里更耐腐蚀。因此，过渡金属 - 金属半导体合金衬里可以在任何随后执行的蚀刻工艺期间用作有效的蚀刻停止层。

17. 发明授权

US09041151B2 Fin eFuse formed by trench silicide process 有权
标题翻译： Fin eFuse通过硅化硅工艺形成
公开(公告)号：US09041151B2
公开(公告)日：2015-05-26
申请号：US13906921
申请日：2013-05-31
申请人： International Business Machines Corporation
发明人： Christian Lavoie , Effendi Leobandung , Dan Moy
IPC分类号： H01L21/306 , H01L21/283 , H01L49/02
CPC分类号： H01L28/00 , H01L21/283 , H01L21/306 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes an enhanced performance electrical fuse formed in a polysilicon fin using a trench silicide process. In one embodiment, at least one semiconductor fin is formed on a dielectric layer present on the surface of a semiconductor substrate. An isolation layer may be formed over the exposed portions of the dielectric layer and the at least one semiconductor fin. At least two contact vias may be formed through the isolation layer to expose the top surface of the semiconductor fin. A continuous silicide may be formed on and substantially below the exposed surfaces of the semiconductor fin extending laterally at least between the at least two contact vias to form an electronic fuse (eFuse). In another embodiment, the at least one semiconductor fin may be subjected to ion implantation to facilitate the formation of silicide.
摘要翻译：提供半导体结构及其制造方法。半导体器件包括使用沟槽硅化物工艺在多晶硅鳍形成的增强型性能电熔丝。在一个实施例中，在存在于半导体衬底的表面上的电介质层上形成至少一个半导体鳍片。可以在电介质层和至少一个半导体鳍片的暴露部分之上形成隔离层。可以通过隔离层形成至少两个接触孔，以暴露半导体鳍的顶表面。连续的硅化物可以形成在半导体鳍片的暴露表面上并且基本上在至少在至少两个接触通孔之间横向延伸以形成电子熔丝（eFuse）的下面。在另一个实施例中，可以对至少一个半导体鳍片进行离子注入以便于形成硅化物。

18. 发明申请

US20150044845A1 METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES 有权
标题翻译：金属半导体合金在接触孔和高岭土中的形成方法
公开(公告)号：US20150044845A1
公开(公告)日：2015-02-12
申请号：US14524650
申请日：2014-10-27
申请人： International Business Machines Corporation
发明人： Christian Lavoie , Zhengwen Li , Ahmet S. Ozcan , Filippos Papadatos , Chengwen Pei , Jian Yu
IPC分类号： H01L29/45 , H01L21/3213 , H01L21/3205 , H01L29/78 , H01L21/321
CPC分类号： H01L29/7833 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/28518 , H01L21/31116 , H01L21/32053 , H01L21/321 , H01L21/32133 , H01L21/76802 , H01L21/76805 , H01L21/76829 , H01L23/535 , H01L29/1054 , H01L29/45 , H01L29/456 , H01L29/458 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7843 , H01L29/7845 , H01L29/7849
摘要： A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.
摘要翻译：提供一种半导体器件，其包括在衬底的沟道区上的栅极结构。源极区域和漏极区域存在于沟道区域的相对侧上。第一金属半导体合金存在于源区和漏区中的至少一个的上表面上。第一金属半导体合金延伸到栅极结构的侧壁。介电层存在于栅极结构和第一金属半导体合金之上。存在通过电介质层到与栅极结构分离的第一金属半导体合金的一部分的开口。第二金属半导体合金存在于开口中，与第一金属半导体合金直接接触，并且具有垂直偏移并位于第一金属半导体合金的上表面上方的上表面。

19. 发明申请

US20140374844A1 METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES 有权
标题翻译：金属半导体合金在接触孔和高岭土中的形成方法
公开(公告)号：US20140374844A1
公开(公告)日：2014-12-25
申请号：US14483923
申请日：2014-09-11
申请人： International Business Machines Corporation
发明人： Christian Lavoie , Zhengwen Li , Ahmet S. Ozcan , Filippos Papadatos , Chengwen Pei , Jian Yu
IPC分类号： H01L29/49 , H01L29/78 , H01L29/45
CPC分类号： H01L29/7833 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/28518 , H01L21/31116 , H01L21/32053 , H01L21/321 , H01L21/32133 , H01L21/76802 , H01L21/76805 , H01L21/76829 , H01L23/535 , H01L29/1054 , H01L29/45 , H01L29/456 , H01L29/458 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7843 , H01L29/7845 , H01L29/7849
摘要： A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.
摘要翻译：提供一种半导体器件，其包括在衬底的沟道区上的栅极结构。源极区域和漏极区域存在于沟道区域的相对侧上。第一金属半导体合金存在于源区和漏区中的至少一个的上表面上。第一金属半导体合金延伸到栅极结构的侧壁。介电层存在于栅极结构和第一金属半导体合金之上。存在通过电介质层到与栅极结构分离的第一金属半导体合金的一部分的开口。第二金属半导体合金存在于开口中，与第一金属半导体合金直接接触，并且具有垂直偏移的上表面并且位于第一金属半导体合金的上表面之上。

20. 发明申请

US20140306291A1 Dual Silicide Process Compatible with Replacement-Metal-Gate 审中-公开
标题翻译：兼容替代金属门的双硅化硅工艺
公开(公告)号：US20140306291A1
公开(公告)日：2014-10-16
申请号：US14010891
申请日：2013-08-27
申请人： International Business Machines Corporation
发明人： Emre Alptekin , Siyuranga O. Koswatta , Christian Lavoie , Ahmet S. Ozcan , Kathryn T. Schonenberg , Paul M. Solomon , Zhen Zhang
IPC分类号： H01L29/417 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/823878 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/41725 , H01L29/41766 , H01L29/66545
摘要： In one aspect, a method for fabricating an electronic device includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined therein. One or more p-FET/n-FET devices are formed in the active areas, each having a p-FET/n-FET gate stack and p-FET/n-FET source and drain regions. A self-aligned silicide is formed in each of the p-FET/n-FET source and drain regions, wherein the self-aligned silicide in each of the p-FET source and drain regions has a thickness T1 and the self-aligned silicide in each of the n-FET source and drain regions having a thickness T2, wherein T1 is less than T2. During a subsequent trench silicidation in the p-FET/n-FET source and drain regions, the trench silicide metal will diffuse through the thinner self-aligned silicide in the p-FET device(s) but not through the thicker self-aligned silicide in the n-FET device(s).
摘要翻译：一方面，电子设备的制造方法包括以下步骤。提供晶片，其具有限定在其中的至少一个第一有源区和至少一个第二有源区。在有源区域中形成一个或多个p-FET / n-FET器件，每个具有p-FET / n-FET栅极堆叠和p-FET / n-FET源极和漏极区域。在p-FET / n-FET源极和漏极区中的每一个中形成自对准硅化物，其中p-FET源极和漏极区中的每一个中的自对准硅化物具有厚度T1和自对准硅化物在每个具有厚度T2的n-FET源极和漏极区域中，其中T1小于T2。在p-FET / n-FET源极和漏极区域中的随后的沟槽硅化期间，沟槽硅化物金属将扩散通过p-FET器件中较薄的自对准硅化物，但不通过较厚的自对准硅化物在n-FET器件中。

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