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11. 发明授权

US10102134B2 Instruction and logic for run-time evaluation of multiple prefetchers 有权
公开(公告)号：US10102134B2
公开(公告)日：2018-10-16
申请号：US15190231
申请日：2016-06-23
申请人： Intel Corporation
发明人： Zeshan A. Chishti , Christopher B. Wilkerson , Seth Pugsley , Peng-Fei Chuang , Robert L. Scott , Aamer Jaleel , Shih-Lien L. Lu , Kingsum Chow
IPC分类号： G06F9/38 , G06F12/0862 , G06F3/06 , G06F13/40
摘要： A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

12. 发明授权

US09417879B2 Systems and methods for managing reconfigurable processor cores 有权
标题翻译：管理可重构处理器内核的系统和方法
公开(公告)号：US09417879B2
公开(公告)日：2016-08-16
申请号：US13924334
申请日：2013-06-21
申请人： Intel Corporation
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Eugene Gorbatov , Zeshan A. Chishti
IPC分类号： G06F9/38 , G06F9/50
CPC分类号： G06F9/3836 , G06F9/5077 , G06F2209/507 , Y02D10/22 , Y02D10/36
摘要： Systems and methods for managing reconfigurable processor cores. An example processing system comprises a plurality of processor cores; a control register including a plurality of state bits, each state bit indicating a state of a corresponding processor core, the control register further including a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and a core management logic configured to merge a first processor core and a second processor core, responsive to determining that a first state bit corresponding to the first processor core is set, a first inhibit bit corresponding to the first processor core is cleared, a second state bit corresponding to the second processor core is cleared, and a second inhibit bit corresponding to the second processor core is cleared.
摘要翻译：管理可重构处理器内核的系统和方法。一个示例性处理系统包括多个处理器核心; 包括多个状态位的控制寄存器，每个状态位指示对应的处理器核心的状态，所述控制寄存器还包括多个禁止位，每个禁止位指示相应的处理器核心是否被允许与其他处理器核心合并 ; 以及核心管理逻辑，用于响应于确定与所述第一处理器核相对应的第一状态位被设置来合并第一处理器核和第二处理器核，清除与所述第一处理器核相对应的第一禁止位，对应于第二处理器核的状态位被清除，并且与第二处理器核相对应的第二禁止位被清除。

13. 发明授权

US10621094B2 Coarse tag replacement 有权
公开(公告)号：US10621094B2
公开(公告)日：2020-04-14
申请号：US15636072
申请日：2017-06-28
申请人： Intel Corporation
发明人： Zhe Wang , Zeshan A. Chishti , Nagi Aboulenein
IPC分类号： G06F12/08 , G06F12/0846 , G06F12/128 , G06F12/0895
CPC分类号： G06F12/0846 , G06F12/0895 , G06F12/128 , G06F2212/604
摘要： An embodiment of a memory apparatus may include a tag cache to cache tag information, and a memory controller communicatively coupled to the tag cache to determine if a request for a memory line results in a tag cache miss, bring tag information for the missed memory line into the tag cache if the request results in a cache miss, and bring tag information for at least one additional memory line adjacent to the missed memory line into the tag cache if the request results in a cache miss. Additional embodiments are disclosed and claimed.

14. 发明授权

US10261901B2 Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory 有权
公开(公告)号：US10261901B2
公开(公告)日：2019-04-16
申请号：US14865617
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： Zhe Wang , Christopher B. Wilkerson , Zeshan A. Chishti , Seth H. Pugsley , Alaa R. Alameldeen , Shih-Lien L. Lu
IPC分类号： G06F12/00 , G06F12/0811 , G06F3/06 , G06F12/0862 , G06F12/0888 , G06F12/0893 , G06F13/00 , G06F13/28
摘要： An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system memory has a caching level. The apparatus includes a first prediction unit to predict unneeded blocks in the last level cache. The apparatus includes a second prediction unit to predict unneeded blocks in the caching level of the multi-level system memory.

15. 发明申请

US20190004952A1 COARSE TAG REPLACEMENT 审中-公开
公开(公告)号：US20190004952A1
公开(公告)日：2019-01-03
申请号：US15636072
申请日：2017-06-28
申请人： Intel Corporation
发明人： Zhe Wang , Zeshan A. Chishti , Nagi Aboulenein
IPC分类号： G06F12/0846 , G06F12/128
摘要： An embodiment of a memory apparatus may include a tag cache to cache tag information, and a memory controller communicatively coupled to the tag cache to determine if a request for a memory line results in a tag cache miss, bring tag information for the missed memory line into the tag cache if the request results in a cache miss, and bring tag information for at least one additional memory line adjacent to the missed memory line into the tag cache if the request results in a cache miss. Additional embodiments are disclosed and claimed.

16. 发明授权

US09583182B1 Multi-level memory management 有权
标题翻译：多级内存管理
公开(公告)号：US09583182B1
公开(公告)日：2017-02-28
申请号：US15077424
申请日：2016-03-22
申请人： Intel Corporation
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Zhe Wang , Zeshan A. Chishti
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G06F12/0804 , G06F12/0292 , G06F12/0868 , G06F12/0897 , G06F12/1009 , G06F12/1027 , G06F12/12 , G06F2212/1021 , G06F2212/502 , G06F2212/608 , G06F2212/651 , G11C8/00 , G11C11/56 , G11C16/08
摘要： A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far memory addresses mapped to the near memory addresses. The number of entries in the register array is less than the number of pages in near memory. Remapping logic determines that a far memory address of the requested data is absent from the register array and selects an available near memory address from the register array. Remapping logic also initiates writing of the requested data at the far memory address to the selected near memory address. Remapping logic further writes the far memory address to an entry of the register array corresponding to the selected near memory address.
摘要翻译：多级存储器管理电路可重新映射近端和远端存储器之间的数据。在一个实施例中，寄存器阵列存储映射到近存储器地址的近地址和远的存储器地址。寄存器数组中的条目数量小于近内存中的页数。重映射逻辑确定所请求数据的远存储器地址不存在于寄存器阵列中，并从寄存器阵列中选择可用的近地址。重映射逻辑还启动在远存储器地址处将所请求的数据写入所选择的近地址。重映射逻辑进一步将远存储器地址写入对应于所选择的近似存储器地址的寄存器阵列的条目。

17. 发明申请

US20160188474A1 HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY FOR INTER-VM COMMUNICATION FOR NFVS AND OTHER PRODUCER-CONSUMER WORKLOADS 审中-公开
标题翻译：硬件/软件优化提高NFVS和其他生产者消费者工作量的互联网通信的性能和能源
公开(公告)号：US20160188474A1
公开(公告)日：2016-06-30
申请号：US14583389
申请日：2014-12-26
申请人： Intel Corporation
发明人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F9/45558 , G06F12/0813 , G06F12/0833 , G06F12/0893 , G06F12/109 , G06F2009/45595 , G06F2212/1021 , G06F2212/283 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.
摘要翻译：实现硬件/软件协同优化的方法和设备，以提高NFV和其他生产者 - 消费者工作负载之间的VM间通信的性能和能量。该装置包括具有多级缓存层级的多核处理器，包括每个核心的L1和L2高速缓存以及共享的最后一级缓存（LLC）。提供了一个或多个机器级指令，用于主动地将高速缓存行从低级缓存级别降级到更高的高速缓存级别，包括将高速缓存行从L1 / L2高速缓存降级到LLC。还提供了用于在多插槽NUMA架构系统中实现硬件/软件协同优化的技术，其中高速缓存线可以被选择性地降级并被推送到远程插座中的LLC。此外，技术是在多插槽系统中实现早期窥探的技术，以减少在远程插槽上访问高速缓存线时的延迟。

18. 发明申请

US20210119766A1 TECHNOLOGIES FOR MEMORY AND I/O EFFICIENT OPERATIONS ON HOMOMORPHICALLY ENCRYPTED DATA 有权
公开(公告)号：US20210119766A1
公开(公告)日：2021-04-22
申请号：US17133711
申请日：2020-12-24
申请人： Intel Corporation
发明人： Vikram B. Suresh , Rosario Cammarota , Sanu K. Mathew , Zeshan A. Chishti , Raghavan Kumar , Rafael Misoczki
IPC分类号： H04L9/00 , G06F12/0802 , G06N20/00
摘要： Technologies for memory and I/O efficient operations on homomorphically encrypted data are disclosed. In the illustrative embodiment, a cloud compute device is to perform operations on homomorphically encrypted data. In order to reduce memory storage space and network and I/O bandwidth, ciphertext blocks can be manipulated as data structures, allowing operands for operations on a compute engine to be created on the fly as the compute engine is performing other operations, using orders of magnitude less storage space and bandwidth.

19. 发明授权

US10108549B2 Method and apparatus for pre-fetching data in a system having a multi-level system memory 有权
公开(公告)号：US10108549B2
公开(公告)日：2018-10-23
申请号：US14863255
申请日：2015-09-23
申请人： Intel Corporation
发明人： Zhe Wang , Christopher B. Wilkerson , Zeshan A. Chishti , Seth H. Pugsley , Alaa R. Alameldeen , Shih-Lien L. Lu
IPC分类号： G06F12/08 , G06F12/12 , G06F12/0862 , G06F12/0811 , G06F12/084
摘要： A method is described that includes creating a first data pattern access record for a region of system memory in response to a cache miss at a host side cache for a first memory access request. The first memory access request specifies an address within the region of system memory. The method includes fetching a previously existing data access pattern record for the region from the system memory in response to the cache miss. The previously existing data access pattern record identifies blocks of data within the region that have been previously accessed. The method includes pre-fetching the blocks from the system memory and storing the blocks in the cache.

20. 发明授权

US09286224B2 Constraining prefetch requests to a processor socket 有权
标题翻译：将预取请求约束到处理器插槽
公开(公告)号：US09286224B2
公开(公告)日：2016-03-15
申请号：US14090056
申请日：2013-11-26
申请人： Intel Corporation
发明人： Seth H. Pugsley , Robert L. Scott , Zeshan A. Chishti , Peng-Fei Chuang , Khun Ban , Christopher B. Wilkerson , Shih-Lien L. Lu , Kingsum Chow
IPC分类号： G06F12/08 , G06F9/45
CPC分类号： G06F12/0862 , G06F8/4442 , G06F12/0811 , G06F12/0897 , G06F2212/602 , Y02D10/13
摘要： In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括具有一个或多个执行单元的至少一个核，第一高速缓冲存储器和第一高速缓存控制逻辑。第一高速缓存控制逻辑可以被配置为生成预取第一数据的第一预取请求，其中如果第一数据不存在于耦合到第一高速缓存存储器的第二高速缓冲存储器中，则该请求将被中止。描述和要求保护其他实施例。

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