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    • 11. 发明授权
    • Decoding apparatus and decoding method
    • 解码装置和解码方法
    • US08588315B2
    • 2013-11-19
    • US12162688
    • 2007-02-21
    • Zheng Zi LiYong Suk HwangJae Hyeong KimSang Bae Ji
    • Zheng Zi LiYong Suk HwangJae Hyeong KimSang Bae Ji
    • H04L27/28
    • H04L27/2647H04L25/067
    • Provided are a decoding apparatus, a decoding method and a receiving apparatus for decoding in a system supporting an OFDM/OFDMA scheme. The decoding method includes the steps of: receiving phase-modulated signal; performing subcarrier demodulation on the received signal and generating correlation metrics; generating decoding metrics using the correlation metrics; and determining a payload using the largest metric of the decoding metrics and at least one of an average metric and the second largest metric of the decoding metrics. The decoding apparatus includes: a receiving buffer for buffering received phase-modulated signal; a likelihood metric generator for generating decoding metrics corresponding to likelihoods of the received signal buffered in the receiving buffer being determined as respective potential payload values; a mean calculator for calculating an average metric; and a payload determiner for determining a payload using the largest metric of the decoding metrics and at least one of an average metric and the second largest metric of the decoding metrics.
    • 提供一种在支持OFDM / OFDMA方案的系统中进行解码的解码装置,解码方法和接收装置。 解码方法包括以下步骤:接收相位调制信号; 对接收到的信号执行子载波解调并产生相关度量; 使用所述相关度量来生成解码度量; 以及使用所述解码度量的最大度量以及所述解码度量的平均度量和所述第二最大度量中的至少一个来确定有效载荷。 解码装置包括:接收缓冲器,用于缓冲接收到的相位调制信号; 用于产生与在接收缓冲器中缓冲的接收信号的似然性相对应的解码度量的似然度量发生器被确定为相应的潜在有效载荷值; 用于计算平均度量的平均计算器; 以及有效载荷确定器,用于使用解码度量的最大度量以及解码度量的平均度量和第二最大度量中的至少一个来确定有效载荷。
    • 15. 发明授权
    • Memory device with packet command
    • 带数据包命令的内存设备
    • US06256261B1
    • 2001-07-03
    • US09605007
    • 2000-06-27
    • Jae Hyeong Kim
    • Jae Hyeong Kim
    • G11C800
    • G11C7/1084G11C7/1051G11C7/1057G11C7/1072G11C7/1078
    • A memory device, comprising: an interface block for transferring a packet data of selected bits through every data pads at a negative edge and a positive edge of clock signals; a data shift block, in accordance with a load signal from the interface block, for converting the packet data in serial transferred through the interface block and writing the converted data into the core block or converting packet data read from the core block into the serial data and transferring the converted data with a packet type through data pads at a negative edge and a positive edge; and a load signal control means for controlling the load signal to be provided into from the interface block to the data shift block in data read in accordance with a confirming signal for indicating whether the data from the core block is ready to read, or not.
    • 一种存储器件,包括:接口块,用于通过位于时钟信号的负沿和上升沿的每个数据焊盘传送所选位的分组数据; 数据移位块,根据来自接口块的负载信号,用于转换通过接口块传送的串行分组数据,并将转换的数据写入核心块或将从核心块读取的分组数据转换为串行数据 并且通过在负边缘和正边沿的数据焊盘传送具有分组类型的转换数据; 以及负载信号控制装置,用于根据用于指示来自核心块的数据是否准备好读取的确认信号,控制从接口块向数据移位块提供的数据移位块的负载信号。