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11. 发明授权

US07989298B1 Transistor having V-shaped embedded stressor 有权
标题翻译：具有V形嵌入应力的晶体管
公开(公告)号：US07989298B1
公开(公告)日：2011-08-02
申请号：US12692859
申请日：2010-01-25
申请人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
发明人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.
摘要翻译：提供半导体器件和制造该器件的方法。该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

12. 发明申请

US20110183486A1 TRANSISTOR HAVING V-SHAPED EMBEDDED STRESSOR 有权
标题翻译：具有V形嵌入式应力的晶体管
公开(公告)号：US20110183486A1
公开(公告)日：2011-07-28
申请号：US12692859
申请日：2010-01-25
申请人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
发明人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.
摘要翻译：提供半导体器件和制造该器件的方法。该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

13. 发明授权

US07947549B2 Gate effective-workfunction modification for CMOS 有权
标题翻译： CMOS有效功能修改功能
公开(公告)号：US07947549B2
公开(公告)日：2011-05-24
申请号：US12037158
申请日：2008-02-26
申请人： Dae-Gyu Park , Michael P Chudzik , Rashmi Jha , Siddarth A Krishnan , Naim Moumen , Vijay Narayanan , Vamsi Paruchuri
发明人： Dae-Gyu Park , Michael P Chudzik , Rashmi Jha , Siddarth A Krishnan , Naim Moumen , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/785
摘要： CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.
摘要翻译：公开了CMOS电路结构，其中PFET和NFET器件具有由相同的栅极绝缘体材料构成的高k电介质层以及由相同栅极金属材料组成的金属栅极层。 PFET器件具有能够沿p方向移动栅极的有效功能的“p”接口控制层。在本发明的代表性实施例中，“p”界面控制层是氧化铝。 NFET器件可以具有“n”个界面控制层。 “p”和“n”界面控制层的材料是不同的材料。 “p”和“n”界面控制层位于其相应的高k电介质层的相对侧。还公开了制造具有相对定位的“p”和“n”界面控制层的CMOS电路结构的方法。

14. 发明申请

US20110089495A1 APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS 有权
标题翻译：聚束光束植入用于制造阈值电压调节FET的应用
公开(公告)号：US20110089495A1
公开(公告)日：2011-04-21
申请号：US12582139
申请日：2009-10-20
申请人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
发明人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
IPC分类号： H01L29/66 , H01L21/8238
CPC分类号： H01L21/823857
摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.
摘要翻译：提供了包括高k栅介质材料的半导体结构，其具有位于距离高k栅极电介质的上表面3nm以内的至少一个表面阈值电压调整区域。所述至少一个表面阈值电压调整区域通过聚束射束注入步骤形成，其中至少一个阈值电压调节杂质直接形成在所述高k栅极电介质内或从上限的阈值电压调节材料驱动，所述材料随后从聚束束植入步骤后的结构。

15. 发明申请

US20110001195A1 Fabrication of self-aligned CMOS structure 有权
标题翻译：自对准CMOS结构的制作
公开(公告)号：US20110001195A1
公开(公告)日：2011-01-06
申请号：US12883874
申请日：2010-09-16
申请人： Dae-Gyu Park , Michael P. Chudzik , Vijay Narayanan , Vamsi Paruchuri
发明人： Dae-Gyu Park , Michael P. Chudzik , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/823857 , H01L29/785
摘要： A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.
摘要翻译：公开了一种用于制造CMOS结构的方法。该方法包括在NFET器件和PFET器件中的高k栅极绝缘体层的覆盖布置以及NFET器件上的栅极金属层的实现。之后是在NFET器件和PFET器件上的Al层的覆盖布置。该方法还包括在Al层上共享的栅极金属层的布置布置。当PFET器件暴露于热退火时，高k电介质氧化Al层，从而将Al层转变为PFET界面控制层，而在NFET器件中，Al成为金属栅极的一个区域。

16. 发明申请

US20100289088A1 THRESHOLD VOLTAGE IMPROVEMENT EMPLOYING FLUORINE IMPLANTATION AND ADJUSTMENT OXIDE LAYER 有权
标题翻译：使用荧光植入和调整氧化层的阈值电压改进
公开(公告)号：US20100289088A1
公开(公告)日：2010-11-18
申请号：US12465908
申请日：2009-05-14
申请人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
发明人： Weipeng Li , Dae-Gyu Park , Melanie J. Sherony , Jin-Ping Han , Yong Meng Lee
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/823807
摘要： An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.
摘要翻译：可以在为p型场效应晶体管保留的第一区域中形成外延半导体层。形成离子注入掩模层并图案化以在第一区域中提供开口，同时阻挡至少为n型场效应晶体管保留的第二区域。将氟注入到开口中以在第一区域中形成外延氟掺杂半导体层和下面的掺氟半导体层。在第一和第二区域中形成包括高k栅极电介质层和调整氧化物层的复合栅极堆叠。 P型和n型场效应晶体管（FET）分别形成在第一和第二区域中。外延氟掺杂半导体层和下面的掺氟半导体层通过直接在上面的调整氧化物部分来补偿p-FET中阈值电压的降低。

17. 发明申请

US20100044805A1 METAL GATES WITH LOW CHARGE TRAPPING AND ENHANCED DIELECTRIC RELIABILITY CHARACTERISTICS FOR HIGH-k GATE DIELECTRIC STACKS 审中-公开
标题翻译：具有低电荷捕获的金属栅极和用于高k栅介质堆叠的增强的电介质可靠性特性
公开(公告)号：US20100044805A1
公开(公告)日：2010-02-25
申请号：US12609555
申请日：2009-10-30
申请人： Alessandro C. Callegari , Michael P. Chudzik , Barry P. Linder , Renee T. Mo , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Sufi Zafar
发明人： Alessandro C. Callegari , Michael P. Chudzik , Barry P. Linder , Renee T. Mo , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Sufi Zafar
IPC分类号： H01L29/78
CPC分类号： H01L21/28088 , H01L21/28518 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665
摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.
摘要翻译：提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

18. 发明申请

US20100038725A1 CHANGING EFFECTIVE WORK FUNCTION USING ION IMPLANTATION DURING DUAL WORK FUNCTION METAL GATE INTEGRATION 有权
标题翻译：在双功能金属门整合期间使用离子植入改变有效的工作功能
公开(公告)号：US20100038725A1
公开(公告)日：2010-02-18
申请号：US12190220
申请日：2008-08-12
申请人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
发明人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/49 , H01L21/28079 , H01L21/28088 , H01L21/823842 , H01L27/092 , H01L29/4958 , H01L29/517
摘要： Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.
摘要翻译：提出了离子注入来改变双功能金属栅极整合的有效功函数。一种方法可以包括在第一类型场效应晶体管（FET）区域和第二类型FET区域上形成高介电常数（高k）层; 在第一型FET区域和第二类型FET区域上形成具有与第一型FET兼容的第一有效功函数的金属层; 以及通过在第二类型FET区域上将金属注入到金属层中，将第一有效功函数改变为第二类不同的有效功函数。

19. 发明申请

US20100038679A1 FINFET WITH LONGITUDINAL STRESS IN A CHANNEL 有权
标题翻译： FINANCE在通道中具有纵向应力
公开(公告)号：US20100038679A1
公开(公告)日：2010-02-18
申请号：US12191425
申请日：2008-08-14
申请人： KEVIN K. CHAN , Qiqing (Christine) Ouyang , Dae-Gyu Park , Xinhui Wang
发明人： KEVIN K. CHAN , Qiqing (Christine) Ouyang , Dae-Gyu Park , Xinhui Wang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7848
摘要： At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.
摘要翻译：在至少一个半导体鳍片的至少一个沟道区域上形成至少一个栅极电介质，栅电极和栅极帽电介质。在栅电极的侧壁上形成栅极间隔物，在栅电极的两侧露出翅片的端部。半导体鳍片的暴露部分被垂直和横向蚀刻，从而减小端部中的至少一个半导体翅片的高度和宽度。绝缘体层的露出部分也可以凹进。晶格不匹配的半导体材料通过选择性外延生长在至少一个半导体鳍片的剩余端部上，并与外部对准至少一个半导体鳍片。晶格不匹配材料沿着形成在至少一个半导体鳍片上的finFET的沟道施加纵向应力。

20. 发明申请

US20100013021A1 METHOD TO REDUCE THRESHOLD VOLTAGE (Vt) IN SILICON GERMANIUM (SIGE), HIGH-K DIELECTRIC-METAL GATE, P-TYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS 有权
标题翻译：降低硅锗（SIGE），高K介电金属栅，P型金属氧化物半导体场效应晶体管的阈值电压（Vt）的方法
公开(公告)号：US20100013021A1
公开(公告)日：2010-01-21
申请号：US12176634
申请日：2008-07-21
申请人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
发明人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
IPC分类号： H01L29/78 , H01L27/092 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/2652 , H01L21/823807 , H01L29/1054
摘要： Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).
摘要翻译：公开了具有最佳阈值电压（Vt）的p型硅锗（SiGe），高k电介质金属栅极，金属氧化物半导体场效应晶体管（PFET），互补金属氧化物半导体（CMOS）器件其包括PFET和形成PFET单独和CMOS器件的方法。实施例将带负电荷的离子（例如，氟（F），氯（Cl），溴（Br），碘（I）等）并入PFET的高k栅介质材料中，以便选择性地调节 PFET的负Vt（即，以减小PFET的负Vt）。

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