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    • 18. 发明授权
    • Method of fabricating one or more tiers of an integrated circuit
    • 制造集成电路的一层或多层的方法
    • US06730617B2
    • 2004-05-04
    • US10132530
    • 2002-04-24
    • Kenneth Raymond Carter
    • Kenneth Raymond Carter
    • H01L2131
    • H01L21/76817H01L21/31695H01L21/76838
    • A process for forming a portion of an integrated circuit includes placing a layer of material on a substrate, in which the material includes a polymeric composition or a precursor to a dielectric composition. The material is contacted with a stamping surface having relief structures that define a pattern, so that a patterned layer is formed as a result of the contact, which may include heating the material to mold it. A metal film or layer is then deposited onto the patterned layer. The metal can then be planarized to form a layer of an integrated circuit. A decomposable or sacrificial polymer is preferably included in the material, so that porous dielectric material is formed, thereby leading to a lower dielectric constant of the end product.
    • 用于形成集成电路的一部分的工艺包括将材料层放置在基板上,其中材料包括聚合物组合物或电介质组合物的前体。 材料与具有限定图案的浮雕结构的冲压表面接触,使得由于接触而形成图案化层,其可以包括加热材料以使其成型。 然后将金属膜或层沉积到图案化层上。 然后可以将金属平坦化以形成集成电路的层。 材料中优选包括可分解或牺牲的聚合物,从而形成多孔介电材料,从而导致最终产品的较低的介电常数。